VSC8062 datasheet, PDF - EEWORLD Datasheet

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VSC8062: Description2.5Gb/s 16-Bit Multiplexer/Demultiplexer Chipset; File Size678KB，20 Pages; ManufacturerVitesse Semiconductor Corporation; Websitehttp://www.vitesse.com/

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2.5Gb/s 16-Bit Multiplexer/Demultiplexer Chipset

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VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

VSC8061/VSC8062

Features

• Serial Data Rate up to 2.5Gb/s

• 16-Bit Wide ECL 100K Compatible Parallel Data

Interface

• Differential High-Speed Data Outputs

2.5Gb/s 16-Bit

Multiplexer/Demultiplexer Chipset

• Power Dissipation: VSC8061:2.0W(max),

VSC8062: 1.7W(max)

• Standard ECL Power Supplies: V

= -5.2V,

= -2.0V

• Differential or Single-Ended High-Speed Data and • Commercial (0 C to +70 C) or Industrial (-40 C

to +85

C) Temperature Range

Clock Inputs

• On-Chip Phase Detector (VSC8061 Multiplexer) • Available in 52-Pin Ceramic Leaded Chip Carrier

or 52-Pin Plastic Quad Flat Pack Packages

Functional Description

The VSC8061 and VSC8062 are high-speed interface devices capable of data rates up to 2.5Gb/s. The

devices are fabricated in gallium arsenide using the Vitesse H-GaAs E/D MESFET process to achieve high-

speed and low power dissipation. For ease of system design using these products, both devices use industry-

standard -5.2V and -2V power supplies, and have ECL-compatible I/O for parallel data interfaces. Typical

applications include telecommunication transmission and instrumentation.

VSC8061 Multiplexer

The VSC8061 consists of a 16:1 multiplexer circuit, a phase detector, and a timing circuit which generates

a divide-by-16 clock from the high-speed clock input. The 16:1 multiplexer accepts 16 parallel single-ended

ECL compatible inputs (D0...D15) at data rates up to 156Mb/s and bitwise serializes them into a 2.5Gb/s serial

output (DO/DON). The internal timing of the VSC8061 is referenced to the negative going edge of the high-

speed clock true input (CLK). This clock is divided by 16 and is provided as an output (CLK16/CLK16N). The

setup and hold time of the parallel inputs (D[0:15]) are specified with respect to the falling edge of CLK16, so

that CLK16/CLK16N can be used to clock the data source of D[0:15]. The on-chip phase detector monitors the

phase relationship between the internally generated divide-by-16 clock and an externally supplied low-speed

reference clock input (DCLK/DCLKN). Phase difference between these two clock signals generates an up or

down output (U, D) for phase lock applications. The phase detector can be used as part of an external Phase

Locked Loop (PLL) to implement a clock multiplication function.

In applications where a 2.5GHz system clock is provided, and the phase detector function is not required, it

is recommended to connect one side of the DCLK/DCLKN input to V

through a 50Ω resistor. The U and D

output can be left open and unused.

VSC8062 Demultiplexer

The VSC8062 consists of a 1:16 demultiplexer and timing circuitry which generates a divide-by-16 clock

from the high-speed clock input. The demultiplexer accepts a serial data stream input (DI/DIN) at up to 2.5Gb/s

and deserializes it into 16 parallel single-ended ECL compatible outputs (D[0:15]) at data rates up to 156 Mb/s.

The internal timing of the VSC8062 is referenced to the negative going edge of the high-speed clock true input

(CLK). This clock is divided by 16 and provided as an output (CLK16/ CLK16N). The timing parameters of the

parallel data outputs (D[0:15]) are specified with respect to the falling edge of CLK16, so that CLK16/CLK16N

can be used to clock the destination of D[0:15].

G52069-0, Rev 4.3

05/11/01

VITESSE

SEMICONDUCTOR CORPORATION

• 741 Calle Plano • Camarillo, CA 93012

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

Page 1

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