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MC74ACT109DTR2

Description
J-Kbar Flip-Flop, ACT Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16, TSSOP-16
Categorylogic    logic   
File Size233KB,9 Pages
ManufacturerRochester Electronics
Websitehttps://www.rocelec.com/
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MC74ACT109DTR2 Overview

J-Kbar Flip-Flop, ACT Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16, TSSOP-16

MC74ACT109DTR2 Parametric

Parameter NameAttribute value
MakerRochester Electronics
package instructionTSSOP,
Reach Compliance Codeunknown
seriesACT
JESD-30 codeR-PDSO-G16
length5 mm
Logic integrated circuit typeJ-KBAR FLIP-FLOP
Number of digits2
Number of functions2
Number of terminals16
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output polarityCOMPLEMENTARY
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
propagation delay (tpd)13 ns
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Trigger typePOSITIVE EDGE
width4.4 mm
minfmax125 MHz
MC74AC109, MC74ACT109
Dual JK Positive
Edge−Triggered Flip−Flop
The MC74AC109/74ACT109 consists of two high−speed
completely independent transition clocked JK flip−flops. The clocking
operation is independent of rise and fall times of the clock waveform.
The JK design allows operation as a D flip−flop (refer to
MC74AC74/74ACT74 data sheet) by connecting the J and K inputs
together.
Asynchronous Inputs:
LOW input to S
D
(Set) sets Q to HIGH level
LOW input to C
D
(Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on C
D
and S
D
makes both Q and Q HIGH
http://onsemi.com
16
1
DIP−16
N SUFFIX
CASE 648
Outputs Source/Sink 24 mA
′ACT109
Has TTL Compatible Inputs
V
CC
16
C
D2
15
C
D
16
Q
2
10
Q
Q
J
2
14
J
K
2
13
K
CP
2
12
CP
S
D2
11
S
D
Q
2
9
16
1
SO−16
D SUFFIX
CASE 751B
1
TSSOP−16
DT SUFFIX
CASE 948F
C
D1
J
1
K
1
CP
1
S
D1
Q
1
Q
1
1
C
D1
2
J
1
3
K
1
4
CP
1
5
S
D1
6
Q
1
7
Q
1
8
GND
16
1
EIAJ−16
M SUFFIX
CASE 966
Figure 1. Pinout; 16−Lead Packages Conductors
(Top View)
PIN ASSIGNMENT
PIN
J
1
, J
2
, K
1
, K
2
CP
1
, CP
2
C
D1
, C
D2
S
D1
, S
D2
Q
1
, Q
2
, Q
1
,
Q
2
FUNCTION
Data Inputs
Clock Pulse Inputs
Direct Clear Inputs
Direct Set Inputs
Outputs
ORDERING INFORMATION
Device
MC74AC109N
MC74ACT109N
MC74AC109D
MC74ACT109D
MC74AC109DR2
MC74ACT109DR2
MC74AC109DT
MC74ACT109DT
MC74AC109DTR2
Package
PDIP−16
PDIP−16
SOIC−16
SOIC−16
SOIC−16
SOIC−16
TSSOP−16
TSSOP−16
Shipping
25 Units/Rail
25 Units/Rail
48 Units/Rail
48 Units/Rail
2500 Tape & Reel
2500 Tape & Reel
96 Units/Rail
96 Units/Rail
TSSOP−16 2500 Tape & Reel
MC74ACT109DTR2 TSSOP−16 2500 Tape & Reel
MC74AC109M
MC74ACT109M
MC74AC109MEL
MC74ACT109MEL
EIAJ−16
EIAJ−16
EIAJ−16
EIAJ−16
50 Units/Rail
50 Units/Rail
2000 Tape & Reel
2000 Tape & Reel
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 6 of this data sheet.
©
Semiconductor Components Industries, LLC, 2006
June, 2006
Rev. 6
1
Publication Order Number:
MC74AC109/D

MC74ACT109DTR2 Related Products

MC74ACT109DTR2 MC74AC109DTR2 MC74AC109N MC74AC109D MC74ACT109DT MC74AC109DR2 MC74AC109MEL MC74ACT109M MC74ACT109MEL MC74AC109M
Description J-Kbar Flip-Flop, ACT Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16, TSSOP-16 J-Kbar Flip-Flop, AC Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16, TSSOP-16 J-Kbar Flip-Flop, AC Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, PDIP16, PLASTIC, DIP-16 J-Kbar Flip-Flop, AC Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16, SOIC-16 J-Kbar Flip-Flop, ACT Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16, TSSOP-16 J-Kbar Flip-Flop, AC Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16, SOIC-16 J-Kbar Flip-Flop, AC Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16, EIAJ, SO-16 J-Kbar Flip-Flop, ACT Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16, EIAJ, SO-16 J-Kbar Flip-Flop, ACT Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16, EIAJ, SO-16 J-Kbar Flip-Flop, AC Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16, EIAJ, SO-16
Maker Rochester Electronics Rochester Electronics Rochester Electronics Rochester Electronics Rochester Electronics Rochester Electronics Rochester Electronics Rochester Electronics Rochester Electronics Rochester Electronics
package instruction TSSOP, TSSOP, DIP, SOP, TSSOP, SOP, SOP, SOP, SOP, SOP,
Reach Compliance Code unknown unknown unknown unknown unknown unknown unknown unknown unknown unknow
series ACT AC AC AC ACT AC AC ACT ACT AC
JESD-30 code R-PDSO-G16 R-PDSO-G16 R-PDIP-T16 R-PDSO-G16 R-PDSO-G16 R-PDSO-G16 R-PDSO-G16 R-PDSO-G16 R-PDSO-G16 R-PDSO-G16
length 5 mm 5 mm 19.175 mm 9.9 mm 5 mm 9.9 mm 10.2 mm 10.2 mm 10.2 mm 10.2 mm
Logic integrated circuit type J-KBAR FLIP-FLOP J-KBAR FLIP-FLOP J-KBAR FLIP-FLOP J-KBAR FLIP-FLOP J-KBAR FLIP-FLOP J-KBAR FLIP-FLOP J-KBAR FLIP-FLOP J-KBAR FLIP-FLOP J-KBAR FLIP-FLOP J-KBAR FLIP-FLOP
Number of digits 2 2 2 2 2 2 2 2 2 2
Number of functions 2 2 2 2 2 2 2 2 2 2
Number of terminals 16 16 16 16 16 16 16 16 16 16
Maximum operating temperature 85 °C 85 °C 85 °C 85 °C 85 °C 85 °C 85 °C 85 °C 85 °C 85 °C
Minimum operating temperature -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C -40 °C
Output polarity COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TSSOP TSSOP DIP SOP TSSOP SOP SOP SOP SOP SOP
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH IN-LINE SMALL OUTLINE SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE
propagation delay (tpd) 13 ns 16 ns 16 ns 16 ns 13 ns 16 ns 16 ns 13 ns 13 ns 16 ns
Maximum seat height 1.2 mm 1.2 mm 4.44 mm 1.75 mm 1.2 mm 1.75 mm 2.05 mm 2.05 mm 2.05 mm 2.05 mm
Maximum supply voltage (Vsup) 5.5 V 6 V 6 V 6 V 5.5 V 6 V 6 V 5.5 V 5.5 V 6 V
Minimum supply voltage (Vsup) 4.5 V 2 V 2 V 2 V 4.5 V 2 V 2 V 4.5 V 4.5 V 2 V
Nominal supply voltage (Vsup) 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V
surface mount YES YES NO YES YES YES YES YES YES YES
technology CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
Temperature level INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL
Terminal form GULL WING GULL WING THROUGH-HOLE GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING
Terminal pitch 0.65 mm 0.65 mm 2.54 mm 1.27 mm 0.65 mm 1.27 mm 1.27 mm 1.27 mm 1.27 mm 1.27 mm
Terminal location DUAL DUAL DUAL DUAL DUAL DUAL DUAL DUAL DUAL DUAL
Trigger type POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE
width 4.4 mm 4.4 mm 7.62 mm 3.9 mm 4.4 mm 3.9 mm 5.275 mm 5.275 mm 5.275 mm 5.275 mm
minfmax 125 MHz 125 MHz 125 MHz 125 MHz 125 MHz 125 MHz 125 MHz 125 MHz 125 MHz 125 MHz

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