MC74ACT109MEL datasheet, PDF - EEWORLD Datasheet

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MC74ACT109MEL: DescriptionJ-Kbar Flip-Flop, ACT Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16, EIAJ, SO-16; Categorylogic logic; File Size233KB，9 Pages; ManufacturerRochester Electronics; Websitehttps://www.rocelec.com/

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MC74ACT109MEL Overview

J-Kbar Flip-Flop, ACT Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16, EIAJ, SO-16

MC74ACT109MEL Parametric

Parameter Name	Attribute value
Maker	Rochester Electronics
package instruction	SOP,
Reach Compliance Code	unknown
series	ACT
JESD-30 code	R-PDSO-G16
length	10.2 mm
Logic integrated circuit type	J-KBAR FLIP-FLOP
Number of digits	2
Number of functions	2
Number of terminals	16
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output polarity	COMPLEMENTARY
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
propagation delay (tpd)	13 ns
Maximum seat height	2.05 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Trigger type	POSITIVE EDGE
width	5.275 mm
minfmax	125 MHz

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MC74AC109, MC74ACT109

Dual JK Positive

Edge−Triggered Flip−Flop

The MC74AC109/74ACT109 consists of two high−speed

completely independent transition clocked JK flip−flops. The clocking

operation is independent of rise and fall times of the clock waveform.

The JK design allows operation as a D flip−flop (refer to

MC74AC74/74ACT74 data sheet) by connecting the J and K inputs

together.

Asynchronous Inputs:

LOW input to S

(Set) sets Q to HIGH level

LOW input to C

(Clear) sets Q to LOW level

Clear and Set are independent of clock

Simultaneous LOW on C

and S

makes both Q and Q HIGH

http://onsemi.com

DIP−16

N SUFFIX

CASE 648

•

Outputs Source/Sink 24 mA

•

′ACT109

Has TTL Compatible Inputs

SO−16

D SUFFIX

CASE 751B

TSSOP−16

DT SUFFIX

CASE 948F

GND

EIAJ−16

M SUFFIX

CASE 966

Figure 1. Pinout; 16−Lead Packages Conductors

(Top View)

PIN ASSIGNMENT

, J

, K

, CP

, C

, S

, Q

FUNCTION

Data Inputs

Clock Pulse Inputs

Direct Clear Inputs

Direct Set Inputs

Outputs

ORDERING INFORMATION

Device

MC74AC109N

MC74ACT109N

MC74AC109D

MC74ACT109D

MC74AC109DR2

MC74ACT109DR2

MC74AC109DT

MC74ACT109DT

MC74AC109DTR2

Package

PDIP−16

SOIC−16

TSSOP−16

Shipping

25 Units/Rail

48 Units/Rail

2500 Tape & Reel

96 Units/Rail

TSSOP−16 2500 Tape & Reel

MC74ACT109DTR2 TSSOP−16 2500 Tape & Reel

MC74AC109M

MC74ACT109M

MC74AC109MEL

MC74ACT109MEL

EIAJ−16

50 Units/Rail

2000 Tape & Reel

DEVICE MARKING INFORMATION

See general marking information in the device marking

section on page 6 of this data sheet.

Semiconductor Components Industries, LLC, 2006

June, 2006

−

Rev. 6

Publication Order Number:

MC74AC109/D

MC74ACT109MEL Related Products

	MC74ACT109MEL	MC74AC109DTR2	MC74AC109N	MC74ACT109DTR2	MC74AC109D	MC74ACT109DT	MC74AC109DR2	MC74AC109MEL	MC74ACT109M	MC74AC109M
Description	J-Kbar Flip-Flop, ACT Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16, EIAJ, SO-16	J-Kbar Flip-Flop, AC Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16, TSSOP-16	J-Kbar Flip-Flop, AC Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, PDIP16, PLASTIC, DIP-16	J-Kbar Flip-Flop, ACT Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16, TSSOP-16	J-Kbar Flip-Flop, AC Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16, SOIC-16	J-Kbar Flip-Flop, ACT Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16, TSSOP-16	J-Kbar Flip-Flop, AC Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16, SOIC-16	J-Kbar Flip-Flop, AC Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16, EIAJ, SO-16	J-Kbar Flip-Flop, ACT Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16, EIAJ, SO-16	J-Kbar Flip-Flop, AC Series, 2-Func, Positive Edge Triggered, 2-Bit, Complementary Output, CMOS, PDSO16, EIAJ, SO-16
Maker	Rochester Electronics	Rochester Electronics	Rochester Electronics	Rochester Electronics	Rochester Electronics	Rochester Electronics	Rochester Electronics	Rochester Electronics	Rochester Electronics	Rochester Electronics
package instruction	SOP,	TSSOP,	DIP,	TSSOP,	SOP,	TSSOP,	SOP,	SOP,	SOP,	SOP,
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknow
series	ACT	AC	AC	ACT	AC	ACT	AC	AC	ACT	AC
JESD-30 code	R-PDSO-G16	R-PDSO-G16	R-PDIP-T16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16	R-PDSO-G16
length	10.2 mm	5 mm	19.175 mm	5 mm	9.9 mm	5 mm	9.9 mm	10.2 mm	10.2 mm	10.2 mm
Logic integrated circuit type	J-KBAR FLIP-FLOP	J-KBAR FLIP-FLOP	J-KBAR FLIP-FLOP	J-KBAR FLIP-FLOP	J-KBAR FLIP-FLOP	J-KBAR FLIP-FLOP	J-KBAR FLIP-FLOP	J-KBAR FLIP-FLOP	J-KBAR FLIP-FLOP	J-KBAR FLIP-FLOP
Number of digits	2	2	2	2	2	2	2	2	2	2
Number of functions	2	2	2	2	2	2	2	2	2	2
Number of terminals	16	16	16	16	16	16	16	16	16	16
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
Output polarity	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SOP	TSSOP	DIP	TSSOP	SOP	TSSOP	SOP	SOP	SOP	SOP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	IN-LINE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE	SMALL OUTLINE
propagation delay (tpd)	13 ns	16 ns	16 ns	13 ns	16 ns	13 ns	16 ns	16 ns	13 ns	16 ns
Maximum seat height	2.05 mm	1.2 mm	4.44 mm	1.2 mm	1.75 mm	1.2 mm	1.75 mm	2.05 mm	2.05 mm	2.05 mm
Maximum supply voltage (Vsup)	5.5 V	6 V	6 V	5.5 V	6 V	5.5 V	6 V	6 V	5.5 V	6 V
Minimum supply voltage (Vsup)	4.5 V	2 V	2 V	4.5 V	2 V	4.5 V	2 V	2 V	4.5 V	2 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	YES	YES	NO	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal form	GULL WING	GULL WING	THROUGH-HOLE	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	1.27 mm	0.65 mm	2.54 mm	0.65 mm	1.27 mm	0.65 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
Trigger type	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE
width	5.275 mm	4.4 mm	7.62 mm	4.4 mm	3.9 mm	4.4 mm	3.9 mm	5.275 mm	5.275 mm	5.275 mm
minfmax	125 MHz	125 MHz	125 MHz	125 MHz	125 MHz	125 MHz	125 MHz	125 MHz	125 MHz	125 MHz

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Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

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