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23S05-1DCG8

Description
SOIC-8, Reel
Categorylogic    logic   
File Size289KB,10 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance
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23S05-1DCG8 Overview

SOIC-8, Reel

23S05-1DCG8 Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Lead free
Is it Rohs certified?conform to
Parts packaging codeSOIC
package instructionSOP, SOP8,.25
Contacts8
Manufacturer packaging codeDCG8
Reach Compliance Codecompli
ECCN codeEAR99
series23S
Input adjustmentSTANDARD
JESD-30 codeR-PDSO-G8
JESD-609 codee3
length4.9 mm
Logic integrated circuit typePLL BASED CLOCK DRIVER
MaximumI(ol)0.032 A
Humidity sensitivity level1
Number of functions1
Number of inverted outputs
Number of terminals8
Actual output times4
Maximum operating temperature70 °C
Minimum operating temperature
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP8,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)260
power supply3.3 V
Certification statusNot Qualified
Same Edge Skew-Max(tskwd)0.25 ns
Maximum seat height1.75 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
Temperature levelCOMMERCIAL
Terminal surfaceMatte Tin (Sn) - annealed
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width3.9 mm
minfmax133 MHz
Base Number Matches1
IDT23S05
3.3V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
3.3V ZERO DELAY CLOCK
BUFFER, SPREAD SPECTRUM
COMPATIBLE
FEATURES:
Phase-Lock Loop Clock Distribution
10MHz to 133MHz operating frequency
Distributes one clock input to one bank of five outputs
Zero Input-Output Delay
Output Skew < 250ps
Low jitter <200 ps cycle-to-cycle
IDT23S05-1 for Standard Drive
IDT23S05-1H for High Drive
No external RC network required
Operates at 3.3V V
DD
Power down mode
Spread spectrum compatible
Available in SOIC package
IDT23S05
DESCRIPTION:
The IDT23S05 is a high-speed phase-lock loop (PLL) clock buffer,
designed to address high-speed clock distribution applications. The zero
delay is achieved by aligning the phase between the incoming clock and
the output clock, operable within the range of 10 to 133MHz.
The IDT23S05 is an 8-pin version of the IDT23S09. IDT23S05 accepts
one reference input, and drives out five low skew clocks. The -1H version
of this device operates up to 133MHz frequency and has a higher drive than
the -1 device. All parts have on-chip PLLs which lock to an input clock on
the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT
pad. In the absence of an input clock, the IDT23S05 enters power down.
In this mode, the device will draw less than 12µA for Commercial Tempera-
ture range and less than 25µA for Industrial temperature range
,
the outputs
are tri-stated, and the PLL is not running, resulting in a significant reduction
of power.
The IDT23S05 is characterized for both Industrial and Commercial
operation.
FUNCTIONAL BLOCK DIAGRAM
8
CLKOUT
REF
1
PLL
Control
Logic
3
CLK1
2
CLK2
5
7
CLK3
CLK4
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
c
2010
Integrated Device Technology, Inc.
AUGUST 2010
DSC 6381/7

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