Am29SL400C
Data Sheet
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number
Am29SL400C
Revision
A
Amendment
+5
Issue Date
March 3, 2005
This Page Left Intentionally Blank.
ADVANCE INFORMATION
Am29SL400C
4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 1.8 Volt-only
Super Low Voltage Flash Memory
Distinctive Characteristics
■
Single power supply operation
— 1.65 to 2.2 V for read, program, and erase
operations
— Ideal for battery-powered applications
■
Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specified addresses
■
Manufactured on 0.32 µm process
technology
■
High performance
— Access times as fast as 100 ns
■
Minimum 1,000,000 erase cycle
guarantee per sector
■
20-year data retention at 125°C
■
Package option
— 48-ball FBGA
— 48-pin TSOP
■
Ultra low power consumption (typical
values at 5 MHz)
—
—
—
—
1 µA Automatic Sleep Mode current
1 µA standby mode current
5 mA read current
20 mA program/erase current
■
Compatibility with JEDEC standards
— Pinout and software compatible with
single-power supply Flash
— Superior inadvertent write protection
■
Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
seven 64 Kbyte sectors (byte mode)
— One 8 Kword, two 4 Kword, one 16 Kword, and
seven 32 Kword sectors (word mode)
— Supports full chip erase
— Sector Protection features:
A hardware method of locking a sector to
prevent any program or erase operations
within that sector
Sectors can be locked in-system or via
programming equipment
■
Data# Polling and toggle bits
— Provides a software method of detecting
program or erase operation completion
■
Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting
program or erase cycle completion
■
Erase Suspend/Erase Resume
— Suspends an erase operation to read data
from, or program data to, a sector that is not
being erased, then resumes the erase
operation
Temporary Sector Unprotect feature allows code
changes in previously locked sectors
■
Unlock Bypass Program Command
— Reduces overall programming time when
issuing multiple program command sequences
■
Hardware reset pin (RESET#)
— Hardware method to reset the device to
reading array data
■
Top or bottom boot block configurations
available
This document contains information on a product under development at Advanced Micro Devices. The information is in-
tended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product
without notice.
Publication#
Am29SL400C
Rev:
A
Amendment+5
Refer to AMD’s Website (www.amd.com) for the latest information.
A d v a n c e
I n f o r m a t i o n
General Description
The Am29SL400C is an 4Mbit, 1.8 V volt-only Flash
memory organized as 524,288 bytes or 262,144
words. The device is offered in 48-pin TSOP and
48-ball FBGA packages. The word-wide data (x16)
appears on DQ15–DQ0; the byte-wide (x8) data ap-
pears on DQ7–DQ0. This device is designed to be
programmed and erased in-system with a single 1.8
volt V
CC
supply. No V
PP
is required for write or erase
operations. The device can also be programmed in
standard EPROM programmers.
The standard device offers access times of 100, 110,
120, and 150 ns, allowing high speed microproces-
sors to operate without wait states. To eliminate bus
contention the device has separate chip enable
(CE#), write enable (WE#) and output enable (OE#)
controls.
The device requires only a
single 1.8 volt power
supply
for both read and write functions. Internally
generated and regulated voltages are provided for
the program and erase operations.
The device is entirely command set compatible with
the
JEDEC single-power-supply Flash standard.
Commands are written to the command register
using standard microprocessor write timings. Regis-
ter contents serve as input to an internal state-ma-
chine that controls the erase and programming
circuitry. Write cycles also internally latch addresses
and data needed for the programming and erase op-
erations. Reading data out of the device is similar to
reading from other Flash or EPROM devices.
Device programming occurs by executing the pro-
gram command sequence. This initiates the
Embed-
ded Program
algorithm—an internal algorithm that
automatically times the program pulse widths and
verifies proper cell margin. The
Unlock Bypass
mode facilitates faster programming times by requir-
ing only two write cycles to program data instead of
four.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the
Embedded Erase
algorithm—an internal algorithm that automatically
preprograms the array (if it is not already pro-
grammed) before executing the erase operation.
During erase, the device automatically times the
erase pulse widths and verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle)
status bits.
After a program or erase cycle
has been completed, the device is ready to read
array data or accept another command.
The
sector erase architecture
allows memory sec-
tors to be erased and reprogrammed without affect-
ing the data contents of other sectors. The device is
fully erased when shipped from the factory.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The
hardware sec-
tor protection
feature disables both program and
erase operations in any combination of the sectors of
memory. This can be achieved in-system or via pro-
gramming equipment.
The
Erase Suspend
feature enables the user to put
erase on hold for any period of time to read data
from, or program data to, any sector that is not se-
lected for erasure. True background erase can thus
be achieved.
The
hardware RESET# pin
terminates any opera-
tion in progress and resets the internal state ma-
chine to reading array data. The RESET# pin may be
tied to the system reset circuitry. A system reset
would thus also reset the device, enabling the sys-
tem microprocessor to read the boot-up firmware
from the Flash memory.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the
automatic sleep mode.
The system can also place the device into the
standby mode.
Power consumption is greatly re-
duced in both these modes.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunneling.
The data is programmed using hot electron injection.
2
March 3, 2005
A d v a n c e
I n f o r m a t i o n
Table of Contents
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5
Special Handling Instructions for FBGA Packages ............6
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9
Table 1. Am29SL400C Device Bus Operations ......................... 9
DQ3: Sector Erase Timer ....................................................... 21
Table 6. Write Operation Status ................................................. 22
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 22
Figure 7. Maximum Negative Overshoot Waveform............. 22
Figure 8. Maximum Positive Overshoot Waveform .............. 22
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 23
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 9. I
CC1
Current vs. Time (Showing Active and
Automatic Sleep Currents) ............................................................ 25
Figure 10. Typical I
CC1
vs. Frequency........................................... 25
Word/Byte Configuration ........................................................9
Requirements for Reading Array Data .................................9
Writing Commands/Command Sequences ....................... 10
Program and Erase Operation Status ................................. 10
Standby Mode ............................................................................ 10
Automatic Sleep Mode ............................................................ 10
RESET#: Hardware Reset Pin ............................................... 10
Output Disable Mode ................................................................11
Table 2. Am29SL400CT Top Boot Block Sector
Address Table ...................................................................................... 11
Table 3. Am29SL400CB Bottom Boot Block
Sector Address Table ........................................................................ 11
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 11. Test Setup ......................................................................... 26
Table 7. Test Specifications ............................................................ 26
Key to Switching Waveforms ............................................... 26
Figure 12. Input Waveforms and Measurement Levels .......... 26
Read Operations .......................................................................27
Figure 13. Read Operations Timings ............................................ 27
Hardware Reset (RESET#) ................................................... 28
Figure 14. RESET# Timings ............................................................. 28
Figure 15. BYTE# Timings for Read Operations ...................... 29
Figure 16. BYTE# Timings for Write Operations.................... 29
Autoselect Mode .........................................................................11
Table 4. Am29SL400C Autoselect Codes (High
Voltage Method) ................................................................................. 12
Erase/Program Operations ................................................... 30
Figure 17. Program Operation Timings........................................ 31
Figure 18. Chip/Sector Erase Operation Timings .................... 32
Sector Protection/Unprotection ...........................................12
Temporary Sector Unprotect ................................................12
Figure 1. In-System Sector Protect/Unprotect Algorithms.... 13
Figure 2. Temporary Sector Unprotect Operation................. 14
AC Characteristics
. . . . . . . . . . . . . . . . . . . . . . . 33
Hardware Data Protection .................................................... 14
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 14
Reading Array Data .................................................................. 14
Reset Command ........................................................................ 14
Autoselect Command Sequence ...........................................15
Word/Byte Program Command Sequence ........................15
Figure 3. Program Operation.......................................................... 16
Figure 19. Data# Polling Timings (During Embedded
Algorithms) ......................................................................................... 33
Figure 20. Toggle Bit Timings (During Embedded
Algorithms) ......................................................................................... 33
Figure 21. DQ2 vs. DQ6 .................................................................. 34
Temporary Sector Unprotect ...............................................34
Figure 22. Temporary Sector Unprotect Timing
Diagram................................................................................................ 34
Figure 23. Sector Protect/Unprotect Timing Diagram .......... 35
Chip Erase Command Sequence ...........................................16
Sector Erase Command Sequence .......................................16
Figure 4. Erase Operation ............................................................... 17
Alternate CE# Controlled Erase/Program
Operations ..................................................................................36
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 24. Alternate CE# Controlled Write Operation
Timings ................................................................................................. 37
Command Definitions ............................................................. 18
Table 5. Am29SL400C Command Definitions .......................... 18
Write Operation Status .......................................................... 18
DQ7: Data# Polling .................................................................. 19
Figure 5. Data# Polling Algorithm................................................. 19
RY/BY#: Ready/Busy# ............................................................. 19
DQ6: Toggle Bit I ..................................................................... 20
DQ2: Toggle Bit II .................................................................... 20
Reading Toggle Bits DQ6/DQ2 ........................................... 20
Figure 6. Toggle Bit Algorithm ....................................................... 21
DQ5: Exceeded Timing Limits ...............................................21
Erase and Programming Performance . . . . . . . . 38
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 38
TSOP Pin and BGA Package Capacitance . . . . . 38
Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 39
TS048—48-Pin Standard TSOP ............................................39
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . .40
FBA048—48-Ball Fine-Pitch Ball Grid Array
(FBGA) 6 x 8 mm Package .................................................... 40
Revision Summary. . . . . . . . . . . . . . . . . . . . . . . . . 41
March 3, 2005
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