Data Sheet
FEATURES
7.5 GHz operating frequency
160 ps propagation delay
100 ps output rise/fall
110 fs random jitter
On-chip input terminations
Extended industrial temperature range: −40°C to +125°C
3.3 V power supply (V
CC
− V
EE
)
Ultrafast, SiGe, Open-Collector
HVDS Clock/Data Buffer
ADCLK914
FUNCTIONAL BLOCK DIAGRAM
V
REF
V
T
50Ω
D
D
50Ω
Q
Q
V
CC
ADCLK914
50Ω
50Ω
APPLICATIONS
Clock and data signal restoration
High speed converter clocking
Broadband communications
Cellular infrastructure
High speed line receivers
ATE and high performance instrumentation
Level shifting
Threshold detection
V
EE
06561-001
Figure 1.
GENERAL DESCRIPTION
The ADCLK914 is an ultrafast clock/data buffer fabricated on
the Analog Devices, Inc., proprietary, complementary bipolar
(XFCB-3) silicon-germanium (SiGe) process. The ADCLK914
features high voltage differential signaling (HVDS) outputs
suitable for driving the latest Analog Devices high speed digital-
to-analog converters (DACs). The ADCLK914 has a single,
differential open-collector output.
The ADCLK914 buffer operates up to 7.5 GHz with a 160 ps
propagation delay and adds only 110 fs random jitter (RJ).
The input has a center tapped, 100 Ω, on-chip termination
resistor and accepts LVPECL, CML, CMOS, LVTTL, or LVDS
(ac-coupled only). A V
REF
pin is available for biasing ac-coupled
inputs.
The HVDS output stage is designed to directly drive 1.9 V each
side into 50 Ω terminated to V
CC
for a total differential output
swing of 3.8 V.
The ADCLK914 is available in a 16-lead LFCSP. It is specified
for operation over the extended industrial temperature range of
−40°C to +125°C.
Rev. B
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ADCLK914* PRODUCT PAGE QUICK LINKS
Last Content Update: 11/29/2017
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REFERENCE MATERIALS
Product Selection Guide
•
RF Source Booklet
•
RF, Microwave, and Millimeter Wave IC Selection Guide
2017
Solutions Bulletins & Brochures
•
Digital-to-Analog Converter ICs Solutions Bulletin, Volume
10, Issue 1
Technical Articles
•
Design A Clock-Distribution Strategy With Confidence
•
Speedy A/Ds Demand Stable Clocks
•
Understand the Effects of Clock Jitter and Phase Noise on
Sampled Systems
Tutorials
•
MT-008: Converting Oscillator Phase Noise to Time Jitter
EVALUATION KITS
•
ADCLK914 Evaluation Board
DOCUMENTATION
Application Notes
•
AN-501: Aperture Uncertainty and ADC System
Performance
•
AN-741: Little Known Characteristics of Phase Noise
•
AN-756: Sampled Systems and the Effects of Clock Phase
Noise and Jitter
•
AN-769: Generating Multiple Clock Outputs from the
AD9540
•
AN-823: Direct Digital Synthesizers in Clocking
Applications Time
•
AN-837: DDS-Based Clock Jitter Performance vs. DAC
Reconstruction Filter Performance
•
AN-873: Lock Detect on the ADF4xxx Family of PLL
Synthesizers
•
AN-927: Determining if a Spur is Related to the DDS/DAC
or to Some Other Source (For Example, Switching
Supplies)
•
AN-939: Super-Nyquist Operation of the AD9912 Yields a
High RF Output Signal
Data Sheet
•
ADCLK914: Ultrafast, SiGe, Open-Collector HVDS Clock/
Data Buffer Data Sheet
User Guides
•
UG-058: Setting Up the Evaluation Board for the
ADCLK914
DESIGN RESOURCES
•
ADCLK914 Material Declaration
•
PCN-PDN Information
•
Quality And Reliability
•
Symbols and Footprints
DISCUSSIONS
View all ADCLK914 EngineerZone Discussions.
SAMPLE AND BUY
Visit the product page to see pricing options.
TECHNICAL SUPPORT
Submit a technical question or find your regional support
number.
SOFTWARE AND SYSTEMS REQUIREMENTS
•
AD9739A Native FMC Card / Xilinx Reference Designs
DOCUMENT FEEDBACK
Submit feedback for this data sheet.
TOOLS AND SIMULATIONS
•
ADIsimCLK Design and Evaluation Software
•
ADCLK914 IBIS Model
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ADCLK914
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Table of Contents .............................................................................. 2
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics ............................................................. 3
Absolute Maximum Ratings............................................................ 5
Thermal Performance .................................................................. 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Data Sheet
Typical Performance Characteristics ..............................................7
Applications Information .................................................................9
Power/Ground Layout and Bypassing ........................................9
HVDS Output Stage ......................................................................9
Interfacing to High Speed DACs .................................................9
Optimizing High Speed Performance ........................................9
Random Jitter .................................................................................9
Typical Application Circuits ..................................................... 10
Outline Dimensions ....................................................................... 11
Ordering Guide .......................................................................... 11
REVISION HISTORY
9/2017—Rev. A to Rev. B
Updated Outline Dimensions ....................................................... 11
Changes to Ordering Guide .......................................................... 11
10/2008—Rev. 0 to Rev. A
Changes to Input Low Voltage Parameter, Table 1 ....................... 3
Changes to Output High Voltage Parameter, Table 1 ................ 3
Changes to Output Low Voltage Parameter, Table 1 .................. 3
Output Differential Range Parameter, Table 1 ............................ 3
Changes to Absolute Maximum Ratings Section ........................ 5
7/2008—Revision 0: Initial Version
Rev. B | Page 2 of 11
Data Sheet
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
V
CC
= 3.3 V, V
EE
= 0 V, T
A
= −40°C to +125°C. All outputs terminated through 50 Ω to V
CC
, unless otherwise noted.
Table 1.
Parameter
DC INPUT CHARACTERISTICS
Input High Voltage
Input Low Voltage
Input Differential Range
Symbol
V
IH
V
IL
V
ID
Min
V
EE
+ 1.65
V
EE
0.2
0.2
Input Capacitance
Input Resistance
Differential Mode
Common Mode
Input Bias Current
DC OUTPUT CHARACTERISTICS
Output High Voltage
Output Low Voltage
Output Differential Range
Reference Voltage
Output Voltage
Output Resistance
AC PERFORMANCE
Operating Frequency
Propagation Delay
Propagation Delay Temperature
Coefficient
Propagation Delay Skew (Device
to Device)
Output Rise Time
Output Fall Time
Wideband Random Jitter
1
Additive Phase Noise
622.08 MHz
C
IN
0.4
50
100
50
20
V
CC
− 0.55
V
CC
− 2.75
1.54
V
CC
− 0.40
V
CC
− 2.35
1.95
(V
CC
+ 1)/2
250
7.5
t
PD
127
158
140
65
t
R
t
F
RJ
100
80
110
−132
−143
−151
−156
−157
−156
−133
−143
−153
−158
−159
−158
125
95
202
V
CC
− 0.25
V
CC
− 1.9
2.22
Typ
Max
V
CC
V
CC
− 0.2
3.4
2.8
Unit
V
V
V p-p
V p-p
pF
Ω
Ω
kΩ
µA
V
V
V
V
Ω
GHz
ps
fs/°C
ps
ps
ps
fs rms
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
V
ID
= 1.6 V p-p
ADCLK914
Test Conditions/Comments
T
A
= −40°C to +85°C
(±1.7 V between input pins)
T
A
= 85°C to 125°C
(±1.4 V between input pins)
Open termination
V
OH
V
OL
V
OD
V
REF
−500 μA to +500 μA
>1.1 V differential output swing,
V
CC
= 3.3 V ± 10%
V
CC
= 3.3 V ± 10%,V
ICM
= V
REF
,
V
ID
= 1.6 V p-p
20%/80%
80%/20%
V
ID
= 1.6 V p-p, 6 V/ns, V
ICM
= 1.85 V
@10 Hz offset
@100 Hz offset
@1 kHz offset
@10 kHz offset
@100 kHz offset
>1 MHz offset
@10 Hz offset
@100 Hz offset
@1 kHz offset
@10 kHz offset
@100 kHz offset
>1 MHz offset
245.76 MHz
Rev. B | Page 3 of 11
ADCLK914
Parameter
122.88 MHz
Symbol
Min
Typ
−150
−156
−160
−161
−161
−160
Max
Unit
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
V
mA
mA
ps/V
dB
Data Sheet
Test Conditions/Comments
@10 Hz offset
@100 Hz offset
@1 kHz offset
@10 kHz offset
@100 kHz offset
>1 MHz offset
POWER SUPPLY
Supply Voltage Requirement
Power Supply Current
Negative Supply Current
Positive Supply Current
Power Supply Rejection
2
Output Swing Supply Rejection
3
1
2
V
CC
I
VEE
I
VCC
PSR
VCC
2.97
66
34
111
55
13
−15
3.63
150
73
Includes output current
V
CC
= 3.3 V ± 10%
V
CC
= 3.3 V ± 10%
Calculated from SNR of ADC method. See Figure 8 for rms jitter vs. input slew rate.
Change in t
PD
per change in V
CC
.
3
Change in output swing per change in V
CC
.
Rev. B | Page 4 of 11
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