SHARC Processors
ADSP-21367/ADSP-21368/ADSP-21369
SUMMARY
High performance 32-bit/40-bit floating-point processor
optimized for high performance audio processing
Single-instruction, multiple-data (SIMD) computational
architecture
On-chip memory—2M bits of on-chip SRAM and 6M bits of
on-chip mask programmable ROM
Code compatible with all other members of the SHARC family
The ADSP-21367/ADSP-21368/ADSP-21369 are available
with a 400 MHz core instruction rate with unique audiocen-
tric peripherals such as the digital applications interface,
S/PDIF transceiver, serial ports, 8-channel asynchronous
sample rate converter, precision clock generators, and
more. For complete ordering information, see
Ordering
Guide on Page 58.
DEDICATED AUDIO COMPONENTS
S/PDIF-compatible digital audio receiver/transmitter
4 independent asynchronous sample rate converters (SRC)
16 PWM outputs configured as four groups of four outputs
ROM-based security features include
JTAG access to memory permitted with a 64-bit key
Protected memory regions that can be assigned to limit
access under program control to sensitive code
PLL has a wide variety of software and hardware multi-
plier/divider ratios
Available in 256-ball BGA_ED and 208-lead LQFP_EP
packages
Internal Memory
SIMD Core
Instruction
Cache
5 stage
Sequencer
Block 0
RAM/ROM
Block 1
RAM/ROM
Block 2
RAM
Block 3
RAM
DAG1/2
Timer
DMD
64-BIT
S
DMD 64-BIT
B0D
64-BIT
B1D
64-BIT
B2D
64-BIT
B3D
64-BIT
PEx
PEy
PMD
64-BIT
Core Bus
Cross Bar
Internal Memory I/F
PMD 64-BIT
EPD BUS 32-BIT
IOD0 32-BIT
FLAGx/IRQx/
TMREXP
JTAG
PERIPHERAL BUS
32-BIT
IOD1
32-BIT
IOD0 BUS
MTM
PERIPHERAL BUS
EP
CORE PCG
FLAGS C-D
TIMER
2-0
TWI
SPI/B
UART
1-0
S/PDIF PCG
Tx/Rx A-D
ASRC IDP/ SPORT
7-0
3-0 PDAP
7-0
CORE PWM
FLAGS 3-0
AMI
SDRAM
DPI Routing/Pins
DAI Routing/Pins
External Port Pin MUX
DPI Peripherals
DAI Peripherals
Peripherals
External
Port
Figure 1. Functional Block Diagram
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009
Analog Devices, Inc. All rights reserved.
ADSP-21367/ADSP-21368/ADSP-21369
TABLE OF CONTENTS
Summary ............................................................... 1
Dedicated Audio Components .................................... 1
General Description ................................................. 3
SHARC Family Core Architecture ............................ 4
Family Peripheral Architecture ................................ 7
I/O Processor Features ......................................... 10
System Design .................................................... 10
Development Tools ............................................. 11
Additional Information ........................................ 12
Pin Function Descriptions ....................................... 13
Specifications ........................................................ 16
Operating Conditions .......................................... 16
Electrical Characteristics ....................................... 17
Package Information ........................................... 18
ESD Caution ...................................................... 18
Maximum Power Dissipation ................................. 18
Absolute Maximum Ratings ................................... 18
Timing Specifications ........................................... 18
Output Drive Currents ......................................... 48
Test Conditions .................................................. 48
Capacitive Loading .............................................. 48
Thermal Characteristics ........................................ 50
256-Ball BGA_ED Pinout ......................................... 51
208-Lead LQFP_EP Pinout ....................................... 54
Package Dimensions ............................................... 56
Surface-Mount Design .......................................... 57
Automotive Products .............................................. 58
Ordering Guide ..................................................... 58
REVISION HISTORY
7/09—Rev. D to Rev. E
Corrected all outstanding document errata. Also replaced core
clock references (CCLK) in the timing specifications with
peripheral clock references (PCLK).
Revised
Functional Block Diagram ................................1
Added
Context Switch ...............................................5
Added
Universal Registers ..........................................5
Clarified VCO operations. See
Voltage Controlled Oscillator .................................... 18
Corrected the pins names for the DAI and DPI in
256-Ball BGA_ED Pinout ......................................... 51
208-Lead LQFP_EP Pinout ....................................... 54
Added 366 MHz LQFP EPAD models for the ADSP-21367 and
ADSP-21369. For additional specifications for these models,
refer to the following:
Specifications ......................................................... 16
Clock Input ........................................................... 21
SDRAM Interface Timing (166 MHz SDCLK) ............... 28
Serial Ports ............................................................ 34
Ordering Guide ...................................................... 58
Rev. E
| Page 2 of 60 | July 2009
ADSP-21367/ADSP-21368/ADSP-21369
GENERAL DESCRIPTION
The ADSP-21367/ADSP-21368/ADSP-21369 SHARC
®
proces-
sors are members of the SIMD SHARC family of DSPs that
feature Analog Devices’ Super Harvard Architecture. These pro-
cessors are source code-compatible with the ADSP-2126x and
ADSP-2116x DSPs as well as with first generation ADSP-2106x
SHARC processors in SISD (single-instruction, single-data)
mode. The processors are 32-bit/40-bit floating-point proces-
sors optimized for high performance automotive audio
applications with its large on-chip SRAM, mask programmable
ROM, multiple internal buses to eliminate I/O bottlenecks, and
an innovative digital applications interface (DAI).
As shown in the functional block diagram
on Page 1,
the
processors use two computational units to deliver a significant
performance increase over the previous SHARC processors on a
range of DSP algorithms. Fabricated in a state-of-the-art, high
speed, CMOS process, the ADSP-21367/ADSP-21368/
ADSP-21369 processors achieve an instruction cycle time of up
to 2.5 ns at 400 MHz. With its SIMD computational hardware,
the processors can perform 2.4 GFLOPS running at 400 MHz.
Table 1
shows performance benchmarks for these devices.
Table 1. Processor Benchmarks (at 400 MHz)
Speed
Benchmark Algorithm
(at 400 MHz)
1024 Point Complex FFT (Radix 4, with reversal) 23.2
μs
FIR Filter (per tap)
1
1.25 ns
1
IIR Filter (per biquad)
5.0 ns
Matrix Multiply (pipelined)
[3×3] × [3×1]
11.25 ns
[4×4] × [4×1]
20.0 ns
Divide (y/x)
8.75 ns
Inverse Square Root
13.5 ns
1
Table 2. ADSP-2136x Family Features
1
(Continued)
ADSP-21369/
ADSP-21369W
8
Yes
Yes
2
Yes
1
32/16/8 bits
2
Yes
128 dB
256 Ball-
BGA,
208-Lead
LQFP_EP
256 Ball-
BGA
256 Ball-
BGA,
208-Lead
LQFP_EP
ADSP-21367
ADSP-21368
Feature
Serial Ports
IDP
DAI
UART
DAI and DPI
S/PDIF Transceiver
AMI Interface Bus Width
SPI
TWI
SRC Performance
Package
1
W = Automotive grade product. See
Automotive Products on Page 58
for more
information.
2
Audio decoding algorithms include PCM, Dolby Digital EX, Dolby Prologic IIx,
DTS 96/24, Neo:6, DTS ES, MPEG-2 AAC, MP3, and functions like bass
management, delay, speaker equalization, graphic equalization, and more.
Decoder/post-processor algorithm combination support varies depending upon
the chip version and the system configurations. Please visit www.analog.com for
complete information.
Assumes two files in multichannel SIMD mode.
Table 2. ADSP-2136x Family Features
1
ADSP-21369/
ADSP-21369W
ADSP-21367
ADSP-21368
The diagram
on Page 1
shows the two clock domains that make
up the ADSP-21367/ADSP-21368/ADSP-21369 processors. The
core clock domain contains the following features.
• Two processing elements (PEx, PEy), each of which com-
prises an ALU, multiplier, shifter, and data register file
• Data address generators (DAG1, DAG2)
• Program sequencer with instruction cache
• PM and DM buses capable of supporting 2x64-bit data
transfers between memory and the core at every core pro-
cessor cycle
• One periodic interval timer with pinout
• On-chip SRAM (2M bit)
• On-chip mask-programmable ROM (6M bit)
• JTAG test access port for emulation and boundary scan.
The JTAG provides software debug through user break-
points which allows flexible exception handling.
Feature
Frequency
RAM
ROM
2
Audio Decoders in ROM
Pulse-Width Modulation
S/PDIF
SDRAM Memory Bus Width
400 MHz
2M bits
6M bits
Yes
Yes
Yes
32/16 bits
Rev. E
| Page 3 of 60 | July 2009
ADSP-21367/ADSP-21368/ADSP-21369
The block diagram of the ADSP-21368
on Page 1
also shows the
peripheral clock domain (also known as the I/O processor) and
contains the following features:
• IOD0 (peripheral DMA) and IOD1 (external port DMA)
buses for 32-bit data transfers
• Peripheral and external port buses for core connection
• External port with an AMI and SDRAM controller
• 4 units for PWM control
• 1 MTM unit for internal-to-internal memory transfers
• Digital applications interface that includes four precision
clock generators (PCG), a input data port (IDP) for serial
and parallel interconnect, an S/PDIF receiver/transmitter,
four asynchronous sample rate converters, eight serial
ports, a flexible signal routing unit (DAI SRU).
• Digital peripheral interface that includes three timers, a 2-
wire interface, two UARTs, two serial peripheral interfaces
(SPI), 2 precision clock generators (PCG) and a flexible sig-
nal routing unit (DPI SRU).
SHARC FAMILY CORE ARCHITECTURE
The ADSP-21367/ADSP-21368/ADSP-21369 are code compati-
ble at the assembly level with the ADSP-2126x, ADSP-21160,
and ADSP-21161, and with the first generation ADSP-2106x
SHARC processors. The ADSP-21367/ADSP-21368/
ADSP-21369 processors share architectural features with the
ADSP-2126x and ADSP-2116x SIMD SHARC processors, as
shown in
Figure 2
and detailed in the following sections.
S
JTAG
FLAG
TIMER INTERRUPT CACHE
SIMD Core
PM DATA 48
DMD/PMD 64
5 STAGE
PROGRAM SEQUENCER
PM ADDRESS 24
DAG1
16x32
DAG2
16x32
PM ADDRESS 32
DM ADDRESS 32
PM DATA 64
SYSTEM
I/F
USTAT
4x32-BIT
PX
64-BIT
DM DATA 64
MULTIPLIER
SHIFTER
ALU
RF
Rx/Fx
PEx
16x40-BIT
DATA
SWAP
RF
Sx/SFx
PEy
16x40-BIT
ALU
SHIFTER
MULTIPLIER
MRF
80-BIT
MRB
80-BIT
ASTATx
STYKx
ASTATy
STYKy
MSB
80-BIT
MSF
80-BIT
Figure 2. SHARC Core Block Diadram
Rev. E
| Page 4 of 60 | July 2009
ADSP-21367/ADSP-21368/ADSP-21369
SIMD Computational Engine
The processors contain two computational processing elements
that operate as a single-instruction, multiple-data (SIMD)
engine. The processing elements are referred to as PEX and PEY
and each contains an ALU, multiplier, shifter, and register file.
PEX is always active, and PEY may be enabled by setting the
PEYEN mode bit in the MODE1 register. When this mode is
enabled, the same instruction is executed in both processing ele-
ments, but each processing element operates on different data.
This architecture is efficient at executing math intensive DSP
algorithms.
Entering SIMD mode also has an effect on the way data is trans-
ferred between memory and the processing elements. When in
SIMD mode, twice the data bandwidth is required to sustain
computational operation in the processing elements. Because of
this requirement, entering SIMD mode also doubles the band-
width between memory and the processing elements. When
using the DAGs to transfer data in SIMD mode, two data values
are transferred with each access of memory or the register file.
The data bus exchange register (PX) permits data to be passed
between the 64-bit PM data bus and the 64-bit DM data bus, or
between the 40-bit register file and the PM data bus. These reg-
isters contain hardware to handle the data width difference.
Timer
A core timer that can generate periodic software Interrupts. The
core timer can be configured to use FLAG3 as a timer expired
signal
Single-Cycle Fetch of Instruction and Four Operands
The ADSP-21367/ADSP-21368/ADSP-21369 feature an
enhanced Harvard architecture in which the data memory
(DM) bus transfers data and the program memory (PM) bus
transfers both instructions and data (see
Figure 2 on Page 4).
With separate program and data memory buses and on-chip
instruction cache, the processors can simultaneously fetch four
operands (two over each data bus) and one instruction (from
the cache), all in a single cycle.
Independent, Parallel Computation Units
Within each processing element is a set of computational units.
The computational units consist of an arithmetic/logic unit
(ALU), multiplier, and shifter. These units perform all opera-
tions in a single cycle. The three units within each processing
element are arranged in parallel, maximizing computational
throughput. Single multifunction instructions execute parallel
ALU and multiplier operations. In SIMD mode, the parallel
ALU and multiplier operations occur in both processing
elements. These computation units support IEEE 32-bit single-
precision floating-point, 40-bit extended precision floating-
point, and 32-bit fixed-point data formats.
Instruction Cache
The processors include an on-chip instruction cache that
enables three-bus operation for fetching an instruction and four
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This
cache allows full-speed execution of core, looped operations
such as digital filter multiply-accumulates, and FFT butterfly
processing.
Data Address Generators with Zero-Overhead Hardware
Circular Buffer Support
The ADSP-21367/ADSP-21368/ADSP-21369 have two data
address generators (DAGs). The DAGs are used for indirect
addressing and implementing circular data buffers in hardware.
Circular buffers allow efficient programming of delay lines and
other data structures required in digital signal processing, and
are commonly used in digital filters and Fourier transforms.
The two DAGs contain sufficient registers to allow the creation
of up to 32 circular buffers (16 primary register sets, 16 second-
ary). The DAGs automatically handle address pointer
wraparound, reduce overhead, increase performance, and sim-
plify implementation. Circular buffers can start and end at any
memory location.
Data Register File
A general-purpose data register file is contained in each pro-
cessing element. The register files transfer data between the
computation units and the data buses, and store intermediate
results. These 10-port, 32-register (16 primary, 16 secondary)
register files, combined with the ADSP-2136x enhanced Har-
vard architecture, allow unconstrained data flow between
computation units and internal memory. The registers in PEX
are referred to as R0–R15 and in PEY as S0–S15.
Context Switch
Many of the processor’s registers have secondary registers that
can be activated during interrupt servicing for a fast context
switch. The data registers in the register file, the DAG registers,
and the multiplier result registers all have secondary registers.
The primary registers are active at reset, while the secondary
registers are activated by control bits in a mode control register.
Flexible Instruction Set
The 48-bit instruction word accommodates a variety of parallel
operations for concise programming. For example, the
ADSP-21367/ADSP-21368/ADSP-21369 can conditionally exe-
cute a multiply, an add, and a subtract in both processing
elements while branching and fetching up to four 32-bit values
from memory—all in a single instruction.
Universal Registers
These registers can be used for general-purpose tasks. The
USTAT (4) registers allow easy bit manipulations (Set, Clear,
Toggle, Test, XOR) for all system registers (control/status) of
the core.
On-Chip Memory
The processors contain two megabits of internal RAM and six
megabits of internal mask-programmable ROM. Each block can
be configured for different combinations of code and data stor-
age (see
Table 3 on Page 6).
Each memory block supports
single-cycle, independent accesses by the core processor and I/O
Rev. E
| Page 5 of 60 | July 2009
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