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Datasheet> All Categories > Analog mixed-signal IC> Amplifier circuit> SMP04G
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SMP04G

Description
IC 4 CHANNEL, SAMPLE AND HOLD AMPLIFIER, UUC16, Sample and Hold Circuit
CategoryAnalog mixed-signal IC    Amplifier circuit   
File Size487KB，15 Pages
ManufacturerADI
Websitehttps://www.analog.com
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SMP04G Overview

IC 4 CHANNEL, SAMPLE AND HOLD AMPLIFIER, UUC16, Sample and Hold Circuit

SMP04G Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerADI
Parts packaging codeWAFER
Contacts16
Reach Compliance Codecompliant
ECCN codeEAR99
Amplifier typeSAMPLE AND HOLD CIRCUIT
Maximum analog input voltage17 V
Minimum analog input voltage-17 V
maximum rate of descent0.025 V/s
JESD-30 codeX-XUUC-N16
JESD-609 codee0
Negative supply voltage upper limit-17 V
Number of functions4
Number of terminals16
Package body materialUNSPECIFIED
encapsulated codeDIE
Package shapeUNSPECIFIED
Package formUNCASED CHIP
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
Sample and hold/Track and holdSAMPLE
Maximum slew rate7 mA
Supply voltage upper limit17 V
Nominal supply voltage (Vsup)12 V
surface mountYES
technologyCMOS
Terminal surfaceTIN LEAD
Terminal formNO LEAD
Terminal locationUPPER
Maximum time at peak reflow temperatureNOT SPECIFIED

SMP04G Preview

SMP04–SPECIFICATIONS
(@ V
DD
= +12.0 V, V
SS
= DGND = 0 V, R
L
= No Load, T
A
= Operating Temperature Range
specified in Absolute Maximum Ratings, unless otherwise noted.)
Parameter
Linearity Error
Buffer Offset Voltage
Hold Step
Droop Rate
Output Source Current
1
Output Sink Current
1
Output Voltage Range
LOGIC CHARACTERISTICS
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
DYNAMIC PERFORMANCE
Acquisition Time
3
Acquisition Time
3
Hold Mode Settling Time
Slew Rate
4
Capacitive Load Stability
Analog Crosstalk
SUPPLY CHARACTERISTICS
Power Supply Rejection Ratio
Supply Current
Power Dissipation
2
ELECTRICAL CHARACTERISTICS
Symbol
V
OS
V
HS
∆V/∆t
I
SOURCE
I
SINK
OVR
Conditions
V
IN
= 6 V
V
IN
= 6 V, T
A
= +25°C to +85°C
V
IN
= 6 V, T
A
= –40°C
V
IN
= 6 V, T
A
= +25°C
V
IN
= 6 V
V
IN
= 6 V
R
L
= 20 kΩ
R
L
= 10 kΩ
Min
–10
Typ
0.01
±
2.5
2.5
2
Max
+10
4
5
25
10.0
9.5
Units
%
mV
mV
mV
mV/s
mA
mA
V
V
V
V
µA
µs
µs
µs
µs
V/µs
pF
dB
dB
mA
mW
1.2
0.5
0.06
0.06
2.4
0.5
V
INH
V
INL
I
IN
t
AQ
t
AQ
t
H
SR
C
L
T
A
= +25°C, 0 V to 10 V Step to 0.1%
–40°C
≤
T
A
≤
+85°C
T
A
= +25°C, 0 V to 10 V Step to 0.01%
To 1 mV
R
L
= 20 kΩ
<30% Overshoot
0 V to 10 V Step
10.8 V
≤
V
DD
≤
13.2 V
0.8
1
4.25
5.25
3
3.5
3.75
9
1
4
500
–80
75
4
PSRR
I
DD
P
DIS
60
7
84
= +5.0 V, V
SS
= –5.0 V, DGND = 0.0 V, R
L
= No Load, T
A
= Operating Temperature
Range specified in Absolute Maximum Ratings, unless otherwise noted.)
DD
ELECTRICAL CHARACTERISTICS
(@ V
Parameter
Symbol
V
OS
V
HS
∆V/∆t
R
OUT
I
SOURCE
I
SINK
OVR
V
INH
V
INL
I
IN
t
AQ
t
AQ
t
H
SR
C
L
PSRR
I
DD
P
DIS
Conditions
V
IN
= 0 V
V
IN
= 0 V, T
A
= +25°C to +85°C
V
IN
= 0 V, T
A
= –40°C
V
IN
= 0 V, T
A
= +25°C
V
IN
= 0 V
V
IN
= 0 V
R
L
= 20 kΩ
Min
–10
Typ
0.01
±
2.5
2.5
2
1
Max
+10
4
5
25
Units
%
mV
mV
mV
mV/s
Ω
mA
mA
V
V
V
µA
µs
µs
µs
V/µs
pF
dB
mA
mW
Linearity Error
Buffer Offset Voltage
Hold Step
Droop Rate
Output Resistance
Output Source Current
1
Output Sink Current
1
Output Voltage Range
LOGIC CHARACTERISTICS
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
DYNAMIC PERFORMANCE
Acquisition Time
3
Acquisition Time
3
Hold Mode Settling Time
Slew Rate
5
Capacitive Load Stability
2
1.2
0.5
–3.0
2.4
0.5
+3.0
0.8
1
11
–3 V to +3 V Step to 0.1%
–3 V to +3 V Step to 0.01%
To 1 mV
R
L
= 20 kΩ
<30% Overshoot
±
5 V
≤
V
DD
≤ ±
6 V
3.6
9
1
3
500
60
75
3.5
SUPPLY CHARACTERISTICS
Power Supply Rejection Ratio
Supply Current
Power Dissipation
5.5
55
NOTES
1
Outputs are capable of sinking and sourcing over 20 mA, but linearity and offset are guaranteed at specified load levels.
2
All input control signals are specified with t
R
= t
F
= 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
3
This parameter is guaranteed without test.
4
Slew rate is measured in the sample mode with a 0 V to 10 V step from 20% to 80%.
5
Slew rate is measured in the sample mode with a –3 V to +3 V step from 20% to 80%.
Specifications are subject to change without notice.
–2–
REV. D
SMP04
ABSOLUTE MAXIMUM RATINGS
(T
A
= +25°C unless otherwise noted)
Package Type
16-Lead Cerdip
16-Lead Plastic DIP
16-Lead SO
*
JA
JA
*
JC
Units
°C/W
°C/W
°C/W
V
DD
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, 17 V
V
DD
to V
SS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.7 V, 17 V
V
LOGIC
to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, V
DD
V
IN
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
SS
, V
DD
V
OUT
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
SS
, V
DD
Analog Output Current . . . . . . . . . . . . . . . . . . . . . . .
±
20 mA
(Not Short-Circuit Protected)
Digital Input Voltage to DGND . . . . . . . –0.3 V, V
DD
+ 0.3 V
Operating Temperature Range
EQ, EP, ES . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . +300°C
94
76
92
12
33
27
is specified for worst case mounting conditions, i.e.,
JA
is specified for device
in socket for cerdip and plastic DIP packages;
JA
is specified for device soldered
to printed circuit board for SO package.
CAUTION
1. Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; function operation
at or above this specification is not implied. Exposure to the above maximum
rating conditions for extended periods may affect device reliability.
2. Digital inputs and outputs are protected; however, permanent damage may
occur on unprotected units from high energy electrostatic fields. Keep units in
conductive foam or packaging at all times until ready to use. Use proper antistatic
handling procedures.
3. Remove power before inserting or removing units from their sockets.
PIN CONNECTIONS
16-Lead Cerdip
16-Lead Plastic DIP
16-Lead SO
V
OUT2
1
V
OUT1
2
V
IN1
3
NC 4
16 V
DD
15 V
OUT3
14 V
OUT4
ORDERING GUIDE
Model
SMP04EQ
SMP04EP
SMP04ES
Temperature
Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package
Description
Cerdip-16
PDIP-16
SO-16
Package
Options*
Q-16
N-16
R-16A
13 V
SS
TOP VIEW
V
IN2
5 (Not to Scale) 12 V
IN4
S/H
1
6
S/H
2
7
DGND 8
11 V
IN3
10
S/H
4
9
S/H
3
SMP04
*Q = Cerdip; N = Plastic DIP; R = Small Outline.
NC = NO CONNECT
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the SMP04 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. D
–3–
SMP04
V
OUT1
V
OUT2
V
DD
V
OUT3
V
OUT4
V
IN1
V
IN2
V
SS
V
IN4
V
IN3
S/H
1
S/H
2
DGND
S/H
3
S/H
4
Dice Characteristics
Die Size: 0.80 x 0.120 mil = 9,600 sq. mil
(2.032 x 3.048mm = 6.193 sq. mm)
WAFER TEST LIMITS
Parameter
Buffer Offset Voltage
Hold Step
Droop Rate
Output Source Current
Output Sink Current
Output Voltage Range
(@ V
DD
= +12 V, V
SS
= DGND = 0 V, R
L
= No Load, T
A
= +25 C, unless otherwise noted.)
Symbol
V
OS
V
HS
∆V/∆t
I
SOURCE
I
SINK
OVR
Conditions
V
IN
= +6 V
V
IN
= +6 V
V
IN
= +6 V
V
IN
= +6 V
V
IN
= +6 V
R
L
= 20 kΩ
R
L
= 10 kΩ
SMP04G
Limits
±
10
±
4
25
1.2
0.5
0.06/10.0
0.06/9.5
2.4
0.8
1
10.8 V
≤
V
DD
≤
13.2 V
60
7
84
Units
mV max
mV max
mV/s max
mA min
mA min
V min/max
V min/max
V min
V max
µA
max
dB min
mA max
mW max
LOGIC CHARACTERISTICS
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
SUPPLY CHARACTERISTICS
Power Supply Rejection Ratio
Supply Current
Power Dissipation
V
INH
V
INL
I
IN
PSRR
I
DD
P
DIS
NOTE
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
–4–
REV. D
Typical Performance Characteristics–SMP04
10000
V
DD
= +12V
V
SS
= 0V
V
IN
= +5V
R
L
= 10k
5
V
DD
= +12V
V
SS
= 0V
3
1800
1600
V
DD
= +12V
V
SS
= 0V
DROOP RATE – mV/s
DROOP RATE – mV/s
DROOP RATE – mV/s
0
1
2
3
4 5
6
7 8
INPUT VOLTAGE – Volts
9
10
1000
1400
1
0
–1
100
1200
1000
10
–3
800
600
0
1
2
3 4
5
6 7
8
INPUT VOLTAGE – Volts
9
10
0
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE – C
–5
Figure 1. Droop Rate vs. Temperature
Figure 2. Droop Rate vs. Input
Voltage (T
A
= +25
°
C)
Figure 3. Droop Rate vs. Input
Voltage (T
A
= +125
°
C)
3
2
T
A
= +25 C
V
DD
= +12V
V
SS
= 0V
HOLD STEP – mV
3
2
7
V
DD
= +12V
V
SS
= 0V
V
IN
= +5V
T
A
= +25 C
V
SS
= 0V
6
1
1
SLEW RATE – V/ s
HOLD STEP – mV
0
–SR
5
0
–1
–1
+SR
4
–2
–3
0
1
2
3
4
5
6
7 8
INPUT VOLTAGE – Volts
9
10
–2
–3
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE – C
3
10
11
12
13 14
15
V
DD
– Volts
16
17
18
Figure 4. Hold Step vs. Input Voltage
Figure 5. Hold Step vs. Temperature
Figure 6. Slew Rate vs. V
DD
2
1
V
DD
= +12V
V
SS
= 0V
OFFSET VOLTAGE – mV
20
15
10
5
0
–5
–10
R
L
= 10k
–15
–20
R
L
=
V
DD
= +12V
V
SS
= 0V
4
2
V
DD
= +12V
V
SS
= 0V
R
L
=
0
R
L
= 20k
–2
–4
–6
–8
–10
0
1
2
3
4
5
6
7 8
INPUT VOLTAGE – Volts
9
10
0
1
2
3 4
5
6
7 8
INPUT VOLTAGE – Volts
9
10
R
L
= 10k
OFFSET VOLTAGE – mV
0
R
L
=
R
L
= 20k
R
L
= 20k
–1
–2
R
L
= 10k
–3
–4
0
1
2
3 4
5
6 7
8
INPUT VOLTAGE – Volts
9
10
Figure 7. Offset Voltage vs. Input
Voltage (T
A
= +25
°
C)
Figure 8. Offset Voltage vs. Input
Voltage (T
A
= +125
°
C)
REV. D
–5–
OFFSET VOLTAGE – mV
Figure 9. Offset Voltage vs. Input
Voltage (T
A
= –55
°
C)
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Description IC 4 CHANNEL, SAMPLE AND HOLD AMPLIFIER, UUC16, Sample and Hold Circuit IC 4 CHANNEL, SAMPLE AND HOLD AMPLIFIER, 9 us ACQUISITION TIME, CDIP16, HERMETIC SEALED, CERDIP-16, Sample and Hold Circuit IC 4 CHANNEL, SAMPLE AND HOLD AMPLIFIER, 9 us ACQUISITION TIME, PDIP16, PLASTIC, DIP-16, Sample and Hold Circuit IC 4 CHANNEL, SAMPLE AND HOLD AMPLIFIER, 9 us ACQUISITION TIME, CDIP16, HERMETIC SEALED, CERDIP-16, Sample and Hold Circuit IC 4 CHANNEL, SAMPLE AND HOLD AMPLIFIER, 9 us ACQUISITION TIME, PDSO16, SOIC-16, Sample and Hold Circuit CMOS Quad Sample-and-Hold Amplifier
Is it Rohs certified? incompatible incompatible incompatible incompatible incompatible conform to
Maker ADI ADI ADI ADI ADI ADI
Parts packaging code WAFER DIP DIP DIP SOIC DIE
Contacts 16 16 16 16 16 -
Reach Compliance Code compliant unknown compliant compliant compliant compliant
ECCN code EAR99 EAR99 EAR99 EAR99 EAR99 EAR99
Amplifier type SAMPLE AND HOLD CIRCUIT SAMPLE AND HOLD CIRCUIT SAMPLE AND HOLD CIRCUIT SAMPLE AND HOLD CIRCUIT SAMPLE AND HOLD CIRCUIT SAMPLE AND HOLD CIRCUIT
Maximum analog input voltage 17 V 3 V 3 V 3 V 3 V 7.5 V
Minimum analog input voltage -17 V -3 V -3 V -3 V -3 V -7.5 V
maximum rate of descent 0.025 V/s 0.025 V/s 0.025 V/s 0.025 V/s 0.025 V/s 0.025 V/s
JESD-30 code X-XUUC-N16 R-GDIP-T16 R-PDIP-T16 R-GDIP-T16 R-PDSO-G16 R-XUUC-N15
Negative supply voltage upper limit -17 V -8.5 V -8.5 V -8.5 V -8.5 V -
Number of functions 4 4 4 4 4 4
Number of terminals 16 16 16 16 16 15
Package body material UNSPECIFIED CERAMIC, GLASS-SEALED PLASTIC/EPOXY CERAMIC, GLASS-SEALED PLASTIC/EPOXY UNSPECIFIED
encapsulated code DIE DIP DIP DIP SOP DIE
Package shape UNSPECIFIED RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form UNCASED CHIP IN-LINE IN-LINE IN-LINE SMALL OUTLINE UNCASED CHIP
Peak Reflow Temperature (Celsius) NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
Certification status Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
Sample and hold/Track and hold SAMPLE SAMPLE SAMPLE SAMPLE SAMPLE SAMPLE
Supply voltage upper limit 17 V 8.5 V 8.5 V 8.5 V 8.5 V 17 V
Nominal supply voltage (Vsup) 12 V 5 V 5 V 5 V 5 V 12 V
surface mount YES NO NO NO YES YES
technology CMOS CMOS CMOS CMOS CMOS CMOS
Terminal form NO LEAD THROUGH-HOLE THROUGH-HOLE THROUGH-HOLE GULL WING NO LEAD
Terminal location UPPER DUAL DUAL DUAL DUAL UPPER
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
JESD-609 code e0 e0 e0 e0 e0 -
Maximum slew rate 7 mA 5.5 mA 5.5 mA 5.5 mA 5.5 mA -
Terminal surface TIN LEAD Tin/Lead (Sn/Pb) TIN LEAD TIN LEAD TIN LEAD -
package instruction - HERMETIC SEALED, CERDIP-16 PLASTIC, DIP-16 HERMETIC SEALED, CERDIP-16 SOIC-16 DIE,
Nominal acquisition time - 9 µs 9 µs 9 µs 9 µs 3.6 µs
length - 19.05 mm 20.13 mm 19.05 mm 10.3 mm -
Nominal Negative Supply Voltage (Vsup) - -5 V -5 V -5 V -5 V -
Maximum operating temperature - 125 °C 85 °C 85 °C 85 °C 85 °C
Minimum operating temperature - -55 °C -40 °C -40 °C -40 °C -40 °C
Maximum seat height - 5.08 mm 5.33 mm 5.08 mm 2.65 mm -
Temperature level - MILITARY INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL
Terminal pitch - 2.54 mm 2.54 mm 2.54 mm 1.27 mm -
width - 7.62 mm 7.62 mm 7.62 mm 7.5 mm -

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