Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . +300°C
94
76
92
12
33
27
is specified for worst case mounting conditions, i.e.,
JA
is specified for device
in socket for cerdip and plastic DIP packages;
JA
is specified for device soldered
to printed circuit board for SO package.
CAUTION
1. Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; function operation
at or above this specification is not implied. Exposure to the above maximum
rating conditions for extended periods may affect device reliability.
2. Digital inputs and outputs are protected; however, permanent damage may
occur on unprotected units from high energy electrostatic fields. Keep units in
conductive foam or packaging at all times until ready to use. Use proper antistatic
handling procedures.
3. Remove power before inserting or removing units from their sockets.
PIN CONNECTIONS
16-Lead Cerdip
16-Lead Plastic DIP
16-Lead SO
V
OUT2
1
V
OUT1
2
V
IN1
3
NC 4
16 V
DD
15 V
OUT3
14 V
OUT4
ORDERING GUIDE
Model
SMP04EQ
SMP04EP
SMP04ES
Temperature
Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package
Description
Cerdip-16
PDIP-16
SO-16
Package
Options*
Q-16
N-16
R-16A
13 V
SS
TOP VIEW
V
IN2
5 (Not to Scale) 12 V
IN4
S/H
1
6
S/H
2
7
DGND 8
11 V
IN3
10
S/H
4
9
S/H
3
SMP04
*Q = Cerdip; N = Plastic DIP; R = Small Outline.
NC = NO CONNECT
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the SMP04 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. D
–3–
SMP04
V
OUT1
V
OUT2
V
DD
V
OUT3
V
OUT4
V
IN1
V
IN2
V
SS
V
IN4
V
IN3
S/H
1
S/H
2
DGND
S/H
3
S/H
4
Dice Characteristics
Die Size: 0.80 x 0.120 mil = 9,600 sq. mil
(2.032 x 3.048mm = 6.193 sq. mm)
WAFER TEST LIMITS
Parameter
Buffer Offset Voltage
Hold Step
Droop Rate
Output Source Current
Output Sink Current
Output Voltage Range
(@ V
DD
= +12 V, V
SS
= DGND = 0 V, R
L
= No Load, T
A
= +25 C, unless otherwise noted.)
Symbol
V
OS
V
HS
∆V/∆t
I
SOURCE
I
SINK
OVR
Conditions
V
IN
= +6 V
V
IN
= +6 V
V
IN
= +6 V
V
IN
= +6 V
V
IN
= +6 V
R
L
= 20 kΩ
R
L
= 10 kΩ
SMP04G
Limits
±
10
±
4
25
1.2
0.5
0.06/10.0
0.06/9.5
2.4
0.8
1
10.8 V
≤
V
DD
≤
13.2 V
60
7
84
Units
mV max
mV max
mV/s max
mA min
mA min
V min/max
V min/max
V min
V max
µA
max
dB min
mA max
mW max
LOGIC CHARACTERISTICS
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
SUPPLY CHARACTERISTICS
Power Supply Rejection Ratio
Supply Current
Power Dissipation
V
INH
V
INL
I
IN
PSRR
I
DD
P
DIS
NOTE
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
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