(max) defines a read cycle. Read access time is measured
from the latter of Device Enable, Output Enable, or valid address
to valid data output.
SRAM Read Cycle 1, the Address Access in figure 3a, is
initiated by a change in address inputs while the chip is enabled
with G asserted and Wn deasserted. Valid data appears on data
outputs DQ(7:0) after the specified t
AVQV
is satisfied. Outputs
remain active throughout the entire cycle. As long as Device
Enable and Output Enable are active, the address inputs may
change at a rate equal to the minimum read cycle time (t
AVAV
).
SRAM read Cycle 2, the Chip Enable - Controlled Access in
figure 3b, is initiated by En going active while G remains
asserted, Wn remains deasserted, and the addresses remain
stable for the entire cycle. After the specified t
ETQV
is satisfied,
the eight-bit word addressed by A(18:0) is accessed and appears
at the data outputs DQ(7:0).
SRAM read Cycle 3, the Output Enable - Controlled Access in
figure 3c, is initiated by G going active while En is asserted, Wn
is deasserted, and the addresses are stable. Read access time is
t
GLQV
unless t
AVQV
or t
ETQV
have not been satisfied.
2
WRITE CYCLE
A combination of Wn less than V
IL
(max) and En less than
V
IL
(max) defines a write cycle. The state of G is a “don’t care”
for a write cycle. The outputs are placed in the high-impedance
state when either G is greater than V
IH
(min), or when Wn is less
than V
IL
(max).
Write Cycle 1, the Write Enable-controlled Access is defined by
a write terminated by Wn going high, with En still active. The
write pulse width is defined by t
WLWH
when the write is initiated
by Wn, and by t
ETWH
when the write is initiated by En. Unless
the outputs have been previously placed in the high-impedance
state by G, the user must wait t
WLQZ
before applying data to the
nine bidirectional pins DQ(7:0) to avoid bus contention.
Write Cycle 2, the Chip Enable-controlled Access is defined by
a write terminated by the latter of En going inactive. The write
pulse width is defined by t
WLEF
when the write is initiated by
Wn, and by t
ETEF
when the write is initiated by the En going
active. For the Wn initiated write, unless the outputs have been
previously placed in the high-impedance state by G, the user
must wait t
WLQZ
before applying data to the eight bidirectional
pins DQ(7:0) to avoid bus contention.
OPERATIONAL ENVIRONMENT
The UT9Q512K32E SRAM incorporates features which allows
operation in a limited environment.
Table 2. Operational Environment
Design Specifications
1
Total Dose
Heavy Ion
Error Rate
2
50
<1.1E-9
krad(Si)
Errors/Bit-Day
Notes:
1. The SRAM will not latchup during radiation exposure under recommended
operating conditions.
2. 90% worst case particle environment, Geosynchronous orbit, 100 mils of
Aluminum.
3
ABSOLUTE MAXIMUM RATINGS
1
(Referenced to V
SS
)
SYMBOL
V
DD
V
I/O
T
STG
P
D
T
J
JC
I
I
PARAMETER
DC supply voltage
Voltage on any pin
Storage temperature
Maximum power dissipation
Maximum junction temperature
2
Thermal resistance, junction-to-case
3
DC input current
LIMITS
-0.5 to 7.0V
-0.5 to 7.0V
-65 to +150C
1.0W (per byte)
+150C
10C/W
±
10 mA
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability and performance.
2. Maximum junction temperature may be increased to +175C during burn-in and steady-static life.
3. Test per MIL-STD-883, Method 1012.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
DD
T
C
V
IN
PARAMETER
Positive supply voltage
Case temperature range
DC input voltage
LIMITS
4.5 to 5.5V
(W) Screen - 40C to 105C
0V to V
DD
4
DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)*
-40C to +105C (V
DD
= 5.0V + 10% for (W) screening)
SYMBOL
V
IH
V
IL
V
OL1
V
OL2
V
OH1
V
OH2
C
IN1
C
IO1
I
IN
I
OZ
PARAMETER
High-level input voltage
Low-level input voltage
Low-level output voltage
Low-level output voltage
High-level output voltage
High-level output voltage
Input capacitance
Bidirectional I/O capacitance
Input leakage current
Three-state output leakage current
(TTL)
(TTL)
I
OL
= 8mA, V
DD
=4.5V (TTL)
I
OL
= 200A,V
DD
=4.5V (CMOS)
I
OH
= -4mA,V
DD
=4.5V (TTL)
I
OH
= 200A,V
DD
=4.5V (CMOS)
= 1MHz @ 0V
= 1MHz @ 0V
V
IN
= V
DD
and V
SS,
V
DD
= V
DD
(max)
V
O
= V
DD
and V
SS
V
DD
= V
DD
(max)
G = V
DD
(max)
I
OS2, 3
I
DD
(OP)
Short-circuit output current
V
DD
= V
DD
(max), V
O
= V
DD
V
DD
= V
DD
(max), V
O
= 0V
Inputs: V
IL
= 0.8V,
V
IH
= 2.0V
I
OUT
= 0mA
V
DD
= V
DD
(max)
Inputs: V
IL
= 0.8V,
V
IH
= 2.0V
I
OUT
= 0mA
V
DD
= V
DD
(max)
-40C and
Inputs: V
IL
= V
SS
25C
I
OUT
= 0mA
E1 = V
DD
- 0.5, V
DD
= V
DD
(max)
105C
V
IH
= V
DD
- 0.5V
9
mA
-90
90
mA
-2
-2
2.4
3.0
45
25
2
2
CONDITION
MIN
2.0
0.8
0.4
0.08
MAX
UNIT
V
V
V
V
V
V
pF
pF
A
A
Supply current operating
@ 1MHz
(per byte)
40
mA
I
DD1
(OP)
Supply current operating
@40MHz
(per byte)
70
mA
I
DD2
(SB)
Supply current standby
@0MHz
(per byte)
24
mA
Notes:
* Post-radiation performance guaranteed at 25C per MIL-STD-883 Method 1019.
1. Measured only for initial qualification and after process or design changes that could affect input/output capacitance.
2. Supplied as a design limit but not guaranteed or tested.
3. Not more than one output may be shorted at a time for maximum duration of one second.
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