ADVANCE
INFORMATION
CY14E256L
256-Kbit (32K x 8) nvSRAM
Features
• 25 ns, 35 ns and 45 ns Access Times
• “Hands-off” Automatic
STORE
on Power Down with
only a small capacitor
•
STORE
to QuantumTrap
®
Nonvolatile Elements is
initiated by Software, Hardware or Autostore
®
on
Power-down
•
RECALL
to SRAM Initiated by Software or Power-up
• Unlimited
READ, WRITE
and
RECALL
Cycles
• 10 mA Typical I
CC
at 200 ns Cycle Time
• 1,000,000
STORE
Cycles to QuantumTrap
• 100-Year Data Retention to QuantumTrap
• Single 5V Operation +10%
• Commercial and Industrial Temperature
• SOIC Package
• RoHS Compliance
Functional Description
The Cypress CY14E256L is a fast static RAM with a nonvol-
atile element in each memory cell. The embedded nonvolatile
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM provides
unlimited read and write cycles, while independent, nonvolatile
data resides in the highly reliable QuantumTrap cell. Data
transfers from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at power down.
On power-up, data is restored to the SRAM (the RECALL
operation) from the nonvolatile memory. Both the STORE and
RECALL operations are also available under software control.
A hardware STORE may be initiated with HSB pin.
Logic Block Diagram
OE
CE
WE
Cypress Semiconductor Corporation
Document #: 001-06968 Rev. *A
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised February 22, 2006
ADVANCE
INFORMATION
Pin Configurations
32-Lead SOIC
CY14E256L
WE
NC
CE
NC
OE
Pin Definitions
Pin Name
A
0
–A
14
WE
CE
OE
V
SS
V
CC
HSB
I/O Type
Input
Input
Input
Input
Ground
Description
Address Inputs used to select one of the 131,072 bytes of the nvSRAM.
Write Enable Input, active LOW.
When selected LOW, enables data on the I/O pins to be written to
the address location latched by the falling edge of CE.
Chip Enable Input, active LOW.
When LOW, selects the chip. When HIGH, deselects the chip.
Output Enable, active LOW.
The active LOW OE input enables the data output buffers during read
cycles. Deasserting OE HIGH causes the I/O pins to tri-state.
Ground for the device.
Should be connected to ground of the system.
DQ0-DQ7 Input/Output
Bidirectional Data I/O lines.
Used as input or output lines depending on operation.
Power Supply
Power Supply inputs to the device.
Input/Output
Hardware Store Busy.
When low this output indicates a Hardware Store is in progress. When pulled
low external to the chip it will initiate a nonvolatile STORE operation. A weak internal pull-up resistor
keeps this pin high if not connected. (Connection Optional)
Power Supply
Autostore
®
Capacitor.
Supplies power to nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
No Connect
No Connects.
This pin is not connected to the die.
V
CAP
NC
Device Operation
The CY14E256L nvSRAM is made up of two functional
components paired in the same physical cell. These are a
SRAM memory cell and a nonvolatile QuantumTrap cell. The
SRAM memory cell operates as a standard fast static RAM.
Data in the SRAM can be transferred to the nonvolatile cell
(the STORE operation), or from the nonvolatile cell to SRAM
(the RECALL operation). This unique architecture allows all
cells to be stored and recalled in parallel. During the STORE
and RECALL operations SRAM READ and WRITE operations
are inhibited. The CY14E256L supports unlimited reads and
writes just like a typical SRAM. In addition, it provides unlimited
RECALL operations from the nonvolatile cells and up to
1 million STORE operations.
SRAM Read
The CY14E256L performs a READ cycle whenever CE and
OE are low while WE and HSB are high. The address specified
on pins A
0–14
determines which of the 32,768 data bytes will
be accessed. When the READ is initiated by an address
transition, the outputs will be valid after a delay of t
AA
(READ
cycle #1). If the READ is initiated by CE or OE, the outputs will
be valid at t
ACE
or at t
DOE
, whichever is later (READ cycle #2).
The data outputs will repeatedly respond to address changes
within the t
AA
access time without the need for transitions on
any control input pins, and will remain valid until another
address change or until CE or OE is brought high, or WE or
HSB is brought low.
Document #: 001-06968 Rev. *A
Page 2 of 16
ADVANCE
INFORMATION
SRAM Write
A WRITE cycle is performed whenever CE and WE are low
and HSB is high. The address inputs must be stable prior to
entering the WRITE cycle and must remain stable until either
CE or WE goes high at the end of the cycle. The data on the
common I/O pins I/O
0–7
will be written into the memory if it is
valid t
SD
before the end of a WE controlled WRITE or before
the end of an CE controlled WRITE. It is recommended that
OE be kept high during the entire WRITE cycle to avoid data
bus contention on common I/O lines. If OE is left low, internal
circuitry will turn off the output buffers t
HZWE
after WE goes
low.
CY14E256L
AutoStore Operation
The CY14E256L stores data to nvSRAM using one of three
storage operations. These three operations are Hardware
Store, activated by HSB, Software Store, activated by an
address sequence, and AutoStore, on device power down.
AutoStore operation is a unique feature of QuantumTrap
technology and is enabled by default on the CY14E256L.
During normal operation, the device will draw current from V
CC
to charge a capacitor connected to the V
CAP
pin. This stored
charge will be used by the chip to perform a single STORE
operation. If the voltage on the V
CC
pin drops below V
SWITCH
,
the part will automatically disconnect the V
CAP
pin from V
CC
.
A STORE operation will be initiated with power provided by the
V
CAP
capacitor.
Figure 1
shows the proper connection of the storage capacitor
(V
CAP
) for automatic store operation. Refer to the DC Charac-
teristics table for the size of V
CAP
. The voltage on the V
CAP
pin
is driven to 5V by a charge pump internal to the chip. A pull-up
should be placed on WE to hold it inactive during power-up.
Figure 2. System Power Mode
is the AutoStore Inhibit mode, in which the AutoStore function
is disabled. If the CY14E256L is operated in this configuration,
references to V
CC
should be changed to V
CAP
throughout this
data sheet. In this mode, STORE operations may be triggered
through software control or the HSB pin. It is not permissible
to change between these three options “on the fly”.
Figure 3. AutoStore Inhibit Mode
To reduce unnecessary nonvolatile stores, AutoStore and
Hardware Store operations will be ignored unless at least one
WRITE operation has taken place since the most recent
STORE or RECALL cycle. Software initiated STORE cycles
are performed regardless of whether a WRITE operation has
taken place. The HSB signal can be monitored by the system
to detect an AutoStore cycle is in progress.
Figure 1. AutoStore
®
Mode
In system power mode (Figure
2),
both V
CC
and V
CAP
are
connected to the +5V power supply without the 68-µF
capacitor. In this mode the AutoStore function of the
CY14E256L will operate on the stored system charge as
power goes down. The user must, however, guarantee that
V
CC
does not drop below 3.6V during the 10-ms STORE cycle.
If an automatic STORE on power loss is not required, then V
CC
can be tied to ground and + 5V applied to V
CAP
(Figure
3).
This
Document #: 001-06968 Rev. *A
Hardware STORE (HSB) Operation
The CY14E256L provides the HSB pin for controlling and
acknowledging the STORE operations. The HSB pin can be
used to request a hardware STORE cycle. When the HSB pin
is driven low, the CY14E256L will conditionally initiate a
STORE operation after t
DELAY
. An actual STORE cycle will
only begin if a WRITE to the SRAM took place since the last
Page 3 of 16
ADVANCE
INFORMATION
STORE or RECALL cycle. The HSB pin also acts as an
open-drain driver that is internally driven low to indicate a busy
condition while the STORE (initiated by any means) is in
progress.
SRAM READ and WRITE operations that are in progress
when HSB is driven low by any means are given time to
complete before the STORE operation is initiated. After HSB
goes low, the CY14E256L will continue SRAM operations for
t
DELAY
. During t
DELAY
, multiple SRAM READ operations may
take place. If a WRITE is in progress when HSB is pulled low
it will be allowed a time, t
DELAY
, to complete. However, any
SRAM WRITE cycles requested after HSB goes low will be
inhibited until HSB returns high.
The HSB pin can be used to synchronize multiple
CY14E256Ls while using a single larger capacitor. To operate
in this mode the HSB pin should be connected together to the
HSB pins from the other CY14E256Ls. An external pull-up
resistor to +5V is required since HSB acts as an open-drain
pull-down. The V
CAP
pins from the other CY14E256L parts can
be tied together and share a single capacitor. The capacitor
size must be scaled by the number of devices connected to it.
When any one of the CY14E256Ls detects a power loss and
asserts HSB, the common HSB pin will cause all parts to
request a STORE cycle (a STORE will take place in those
CY14E256Ls that have been written since the last nonvolatile
cycle).
During any STORE operation, regardless of how it was
initiated, the CY14E256L will continue to drive the HSB pin
low, releasing it only when the STORE is complete. Upon
completion of the STORE operation the CY14E256L will
remain disabled until the HSB pin returns high.
If HSB is not used, it should be left unconnected.
CY14E256L
To initiate the software STORE cycle, the following READ
sequence must be performed:
1. Read address 0x0000, Valid READ
2. Read address 0x1555, Valid READ
3. Read address 0x0AAA, Valid READ
4. Read address 0x1FFF, Valid READ
5. Read address 0x10F0, Valid READ
6. Read address 0x0F0F, Initiate STORE cycle
The software sequence may be clocked with CE-controlled
READs or OE-controlled READs. Once the sixth address in
the sequence has been entered, the STORE cycle will
commence and the chip will be disabled. It is important that
READ cycles and not WRITE cycles be used in the sequence,
although it is not necessary that OE be low for the sequence
to be valid. After the t
STORE
cycle time has been fulfilled, the
SRAM will again be activated for READ and WRITE operation.
Software RECALL
Data can be transferred from the nonvolatile memory to the
SRAM by a software address sequence. A software RECALL
cycle is initiated with a sequence of READ operations in a
manner similar to the software STORE initiation. To initiate the
RECALL cycle, the following sequence of CE-controlled
READ operations must be performed:
1. Read address 0x0000, Valid READ
2. Read address 0x1555, Valid READ
3. Read address 0x0AAA, Valid READ
4. Read address 0x1FFF, Valid READ
5. Read address 0x10F0, Valid READ
6. Read address 0x0F0E, Initiate RECALL cycle
Internally, RECALL is a two-step procedure. First, the SRAM
data is cleared, and second, the nonvolatile information is
transferred into the SRAM cells. After the t
RECALL
cycle time
the SRAM will once again be ready for READ and WRITE
operations. The RECALL operation in no way alters the data
in the nonvolatile elements.
Hardware RECALL (Power-up)
During power-up, or after any low-power condition (V
CC
<
V
SWITCH
), an internal RECALL request will be latched. When
V
CC
once again exceeds the sense voltage of V
SWITCH
, a
RECALL cycle will automatically be initiated and will take
t
HRECALL
to complete.
If the CY14E256L is in a WRITE state at the end of power-up
RECALL, the SRAM data will be corrupted. To help avoid this
situation, a 10-Kohm resistor should be connected either
between WE and system V
CC
or between CE and system V
CC
.
Data Protection
The CY14E256L protects data from corruption during
low-voltage conditions by inhibiting all externally initiated
STORE and WRITE operations. The low voltage condition is
detected when V
CC
< V
SWITCH
. If the CY14E256L is in a
WRITE mode (both CE and WE low) at power-up, after a
RECALL, or after a STORE, the WRITE will be inhibited until
a negative transition on CE or WE is detected. This protects
against inadvertent writes during power-up or brown-out
conditions.
Software STORE
Data can be transferred from the SRAM to the nonvolatile
memory by a software address sequence. The CY14E256L
software STORE cycle is initiated by executing sequential
CE-controlled READ cycles from six specific address locations
in exact order. During the STORE cycle an erase of the
previous nonvolatile data is first performed, followed by a
program of the nonvolatile elements. Once a STORE cycle is
initiated, further input and output are disabled until the cycle is
completed.
Because a sequence of READs from specific addresses is
used for STORE initiation, it is important that no other READ
or WRITE accesses intervene in the sequence, or the
sequence will be aborted and no STORE or RECALL will take
place.
Noise Considerations
The CY14E256L is a high-speed memory and so must have a
high-frequency bypass capacitor of approximately 0.1 µF
connected between V
CC
and V
SS
, using leads and traces that
are as short as possible. As with all high-speed CMOS ICs,
careful routing of power, ground, and signals will reduce circuit
noise.
Document #: 001-06968 Rev. *A
Page 4 of 16
ADVANCE
INFORMATION
Low Average Active Power
CMOS technology provides the CY14E256L the benefit of
drawing significantly less current when it is cycled at times
longer than 50 ns.
Figure 4
shows the relationship between
CY14E256L
Figure 5. Current vs. Cycle Time (WRITE)
6. The V
CC
level.
7. I/O loading.
Figure 4. Current vs. Cycle Time (READ)
I
CC
and READ/WRITE cycle time. V
CC
= 3.6V, and chip enable
at maximum frequency. Only standby current is drawn when
the chip is disabled. The overall average current drawn by the
CY14E256L depends on the following items:
1. The duty cycle of chip enable.
2. The overall cycle rate for accesses.
3. The ratio of READs to WRITEs.
4. CMOS vs. TTL Input Levels.
5. The operating temperature.
Table 1. Hardware Mode Selection
CE
H
L
L
X
WE
X
H
L
X
HSB
H
H
H
L
A13–A0
X
X
X
X
Mode
Not Selected
Read SRAM
Write SRAM
Nonvolatile STORE
I/O
Output High-Z
Output Data
Input Data
Output High-Z
Power
Standby
Active
Active
I
CC2
Preventing STOREs
The STORE function can be disabled on the fly by holding HSB
high with a driver capable of sourcing 30 mA at a V
OH
of at
least 2.2V, as it will have to overpower the internal pull-down
device that drives HSB low for 20
µs
at the onset of a STORE.
When the CY14E256L is connected for AutoStore operation
(system V
CC
connected to V
CC
and a 68-µF capacitor on
V
CAP
) and V
CC
crosses V
SWITCH
on the way down, the
CY14E256L will attempt to pull HSB low; if HSB doesn’t
actually get below V
IL
,the part will stop trying to pull HSB low
and abort the STORE attempt.
Document #: 001-06968 Rev. *A
Page 5 of 16
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