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W3EG64128S335D3SG

Description
DDR DRAM Module, 128MX64, 0.7ns, CMOS, ROHS COMPLIANT, DIMM-184
Categorystorage    storage   
File Size295KB,12 Pages
ManufacturerMicrosemi
Websitehttps://www.microsemi.com
Environmental Compliance  
Download Datasheet Parametric View All

W3EG64128S335D3SG Overview

DDR DRAM Module, 128MX64, 0.7ns, CMOS, ROHS COMPLIANT, DIMM-184

W3EG64128S335D3SG Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerMicrosemi
Parts packaging codeDIMM
package instructionDIMM,
Contacts184
Reach Compliance Codeunknown
ECCN codeEAR99
access modeDUAL BANK PAGE BURST
Maximum access time0.7 ns
Other featuresAUTO/SELF REFRESH
JESD-30 codeR-XDMA-N184
memory density8589934592 bit
Memory IC TypeDDR DRAM MODULE
memory width64
Number of functions1
Number of ports1
Number of terminals184
word count134217728 words
character code128000000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize128MX64
Package body materialUNSPECIFIED
encapsulated codeDIMM
Package shapeRECTANGULAR
Package formMICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
self refreshYES
Maximum supply voltage (Vsup)2.7 V
Minimum supply voltage (Vsup)2.3 V
Nominal supply voltage (Vsup)2.5 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formNO LEAD
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
White Electronic Designs
1GB – 2x64Mx64 DDR SDRAM UNBUFFERED
FEATURES
Double-data-rate architecture
Clock speeds of 100MHz, 133MHz, 166MHz and
200MHz
DDR200, DDR266, DDR333 and DDR400
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input.
Auto and self refresh
Serial presence detect
Dual Rank
Power supply:
• V
CC
= V
CCQ
= +2.5V ±0.2V (100, 133 and 166 MHz)
• V
CC
= V
CCQ
= +2.6V ±0.1V (200 MHz)
JEDEC standard 184 pin DIMM package
• JD3 PCB height: 30.48 (1.20") MAX
W3EG64128S-D3
-JD3
ADVANCED*
DESCRIPTION
The W3EG64128S is a 2x64Mx64 Double Data Rate
SDRAM memory module based on 512Mb DDR SDRAM
component. The module consists of sixteen 64Mx8 DDR
SDRAMs in 66 pin TSOP packages mounted on a 184
pin FR4 substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
NOTE: Consult factory for availability of:
• RoHS compliant products
• Vendor source control options
• Industrial temperature option
OPERATING FREQUENCIES
Clock Speed
CL-t
RCD
-t
RP
DDR400 @ CL=3
200MHz
3-3-3
DDR333 @ CL=2.5
166MHz
2.5-3-3
DDR266 @ CL=2
133MHz
2-2-2
DDR266 @ CL=2
133MHz
2-3-3
DDR266 @ CL=2.5
133MHz
2.5-3-3
DDR200 @ CL=2
100MHz
2-2-2
December 2006
Rev. 6
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
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