255MHz, Low J
ITTER
, C
RYSTAL
Oscillator -
TO
-
3.3V LVPECL F
REQUENCY
S
YNTHESIZER
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES APRIL 25, 2015
ICS8431-11
DATASHEET
G
ENERAL
D
ESCRIPTION
The ICS8431-11 is a general purpose clock frequency synthesizer
for IA64/32 application and a member of the HiPerClockS™ family of
High Performance Clock Solutions from ICS. The VCO operates at a
frequency range of 250MHz to 510MHz providing an output frequency
range of 125MHz to 255MHz. The output frequency can be programmed
using the parallel interface, M0 through M8, to the configuration log-
ic. Spread spectrum clocking is programmed via the control inputs
SSC_CTL0 and SSC_CTL1.
Programmable features of the ICS8431-11 support four operational
modes. The four modes are spread spectrum clocking (SSC), non-
spread spectrum clock and two test modes which are controlled by
the SSC_CTL[1:0] pins. Unlike other synthesizers, the ICS8431-11
can immediately change spread-spectrum operation without having
to reset the device.
In SSC mode, the output clock is modulated in order to achieve a
reduction in EMI. In one of the PLL bypass test modes, the PLL is
disconnected as the source to the differential output allowing an
external source to be connected to the TEST_I/O pin. This is useful
for in-circuit testing and allows the differential output to be driven at
a lower frequency throughout the system clock tree. In the other PLL
bypass mode, the oscillator divider is used as the source to both the M
and the Fout divide by 2. This is useful for characterizing the oscillator
and internal dividers.
F
EATURES
•
Fully integrated PLL
•
Differential 3.3V LVPECL output
•
Crystal oscillator interface
•
Output frequency range: 125MHz to 255MHz
•
Crystal input frequency range: 14MHz to 20MHz
•
VCO range: 250MHz to 510MHz
•
Programmable PLL loop divider for generating a variety
of output frequencies
•
Spread Spectrum Clocking (SSC) fixed at 1/2% modulation for
environments requiring ultra low EMI
•
PLL bypass modes supporting in-circuit testing and on-chip func-
tional block characterization
•
Cycle-to-cycle jitter: 30ps (maximum)
•
3.3V supply voltage
•
Lead-Free package available
•
0°C to 85°C ambient operating temperature
B
LOCK
D
IAGRAM
XTAL1
OSC
XTAL2
÷
16
P
IN
A
SSIGMENT
M0
M1
M2
M3
M4
M5
M6
M7
M8
SSC_CTL0
SSC_CTL1
V
EE
TEST_I/O
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
nP_LOAD
V
CC
XTAL2
XTAL1
nc
nc
V
CCA
V
EE
MR
nc
V
CCO
FOUT
nFOUT
V
EE
PLL
PHASE
DETECTOR
VCO
÷
M
÷
2
FOUT
nFOUT
ICS8431-11
TEST_I/O
M0:M8
Configuration
Logic
SSC
Control
Logic
28-Lead SOIC
7.5mm x 18.05mm x 2.25mm package body
M Package
Top View
nP_LOAD
SSC_CTL0
SSC_CTL1
ICS8431EM REVISION D MAY 14, 2014
1
©2014 Integrated Device Technology, Inc.
ICS8431EM-11 Data Sheet
255MHz, Low J
ITTER
, C
RYSTAL
Oscillator -
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
F
UNCTIONAL
D
ESCRIPTION
The ICS8431-11 features a fully integrated PLL and therefore
requires no external components for setting the loop bandwidth.
A 16MHz series-resonant, fundamental crystal is used as the input
to the on-chip oscillator. The output of the oscillator is divided by 16
prior to the phase detector. With a 16MHz crystal this provides a 1MHz
reference frequency. The VCO of the PLL operates over a range of
250MHz to 510MHz. The output of the M divider is also applied to the
phase detector.
The phase detector and the M divider force the VCO output frequency
to be M times the reference frequency by adjusting the VCO control
voltage. Note that for some values of M (either too high or too low), the
PLL will not achieve lock. The output of the VCO is scaled by a divider
prior to being sent to the LVPECL output buffer. The divider provides
a 50% output duty cycle.
The programmable features of the ICS8431-11 support four
output operational modes and a programmable M divider and
output divider. The four output operational modes are spread
spectrum clocking (SSC), non-spread spectrum clock and
two test modes and are controlled by the SSC_CTL[1:0] pins.
The PLL loop divider or M divider is programmed by using inputs M0
through M8. While the nP_LOAD input is held LOW, the data present at
M0:M8 is transparent to the M divider. On the LOW-to-HIGH transition
of nP_LOAD, the M0:M8 data is latched into the M divider and any
further changes at the M0:M8 inputs will not be seen by the M divider
until the next LOW transition on nP_LOAD.
The relationship between the VCO frequency, the crystal frequency
and the M divider is defined as follows:
fxtal x
fVCO =
M
16
The M value and the required values of M0:M8 for programming the
VCO are shown in
Table 3B,
Programmable VCO Frequency Function
Table. The frequency out is defined as follows:
FOUT = fVCO = fxtal x M
2
32
For the ICS8431-11, the output divider equals 2. Valid
M values for which the PLL will achieve lock are defined as:
250
≤
M
≤
510.
ICS8431EM REVISION D MAY 14, 2014
2
©2014 Integrated Device Technology, Inc.
ICS8431EM-11 Data Sheet
255MHz, Low J
ITTER
, C
RYSTAL
Oscillator -
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2, 3, 4, 5,
6, 7
8, 9
10, 11
12, 15, 21
13
14, 27
16, 17
18
19, 23, 24
Name
M0-M6
M7-M8
SSC CTL0,
SSC CTL1
V
EE
TEST I/O
V
CC
nFOUT, FOUT
V
CCO
nc
Input
Input
Input
Power
Input /
Output
Power
Output
Power
Unused
Type
Description
Pulldown M divider inputs. Data latched on LOW-to-HIGH transistion
of nP_LOAD input. LVCMOS / LVTTL pins interface levels.
Pullup
Pullup
SCC control pins. LVTTL / LVCMOS interface levels.
Negative supply pins. Connect all V
EE
pins to board ground.
Programmed as input in PLL bypass mode.
Core supply pins.
Differential outputs for the synthesizer. 3.3V LVPECL interface levels.
Output supply pin.
No connect.
Active High Master Reset. When logic HIGH, the internal dividers are reset causing
the true output FOUT to go low and the inverted output nFOUT to go high. When logic
Pulldown
LOW, the internal dividers and the outputs are enabled. Assertion of MR does not effect
loaded M and T values. LVCMOS / LVTTL interface levels.
Analog supply pin.
20
MR
Input
22
25, 26
V
CCA
XTAL1, XTAL2
Power
Input
Crystal oscillator interface. XTAL1 is the input. XTAL2 is the output.
Parallel load input. Determines when data present at M8:M0
28
nP_LOAD
Input
Pulldown
is loaded into M divider. LVTTL / LVCMOS interface levels.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Pin Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
KΩ
KΩ
ICS8431EM REVISION D MAY 14, 2014
3
©2014 Integrated Device Technology, Inc.
ICS8431EM-11 Data Sheet
255MHz, Low J
ITTER
, C
RYSTAL
Oscillator -
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
T
ABLE
3A. SSC C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Outputs
SSC
Operational Modes
FOUT,
SSC_CTL1 SSC_CTL0
TEST_I/O
nFOUT
fXTAL
÷
16 PLL bypass; oscillator, M and N dividers test
0
0
Internal
Disabled fXTAL
÷
32
mode. NOTE 1
÷
M
fXTAL x M
Hi-Z
Default SSC; Modulation Factor = ½ Percent
0
1
PLL
Enabled
32
PLL Bypass Mode,
1
0
External Disabled
Test Clk
Input
(1MHz≤ Test Clk
≤
200MHz); NOTE 1
fXTAL x M
Hi-Z
No SSC Modulation
1
1
PLL
Disabled
32
NOTE 1: Used for in house debug and characterization.
TEST_I/O
Source
Inputs
T
ABLE
3B. P
ROGRAMMABLE
VCO F
REQUENCY
F
UNCTION
T
ABLE
(NOTE 1)
VCO Frequency
(MHz)
250
251
252
253
•
•
508
509
510
M Count
250
251
252
253
•
•
508
509
510
256
M8
0
0
0
0
•
•
1
1
1
128
M7
1
1
1
1
•
•
1
1
1
64
M6
1
1
1
1
•
•
1
1
1
32
M5
1
1
1
1
•
•
1
1
1
16
M4
1
1
1
1
•
•
1
1
1
8
M3
1
1
1
1
•
•
1
1
1
4
M2
0
0
1
1
•
•
1
1
1
2
M1
1
1
0
0
•
•
0
0
1
1
M0
0
1
0
1
•
•
0
1
0
NOTE 1: Assumes a 16MHz crystal.
ICS8431EM REVISION D MAY 14, 2014
4
©2014 Integrated Device Technology, Inc.
ICS8431EM-11 Data Sheet
255MHz, Low J
ITTER
, C
RYSTAL
Oscillator -
TO
-3.3V LVPECL F
REQUENCY
S
YNTHESIZER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
46.2°C/W (0 lfpm)
-65°C to 150°C
N OT E : S t r e s s e s b e y o n d t h o s e l i s t e d u n d e r A b s o l u t e
Maximum Ratings may cause per manent damage to the
device. These ratings are stress specifications only. Functional oper-
ation of product at these conditions or any conditions beyond those
listed in the
DC Characteristics
or
AC Characteristics
is not implied.
Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= 0°C
TO
85°C
Symbol
V
CC
V
CCO
V
CCA
I
EE
Parameter
Core Supply Voltage
Output Supply Voltage
Analog Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
Maximum Units
3.465
3.465
3.465
140
V
V
V
mA
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= 0°C
TO
85°C
Symbol
V
IH
Parameter
M0:M8, SSC_CTL0,
Input High Voltage SSC_CTL1, MR,
TEST_I/O, nP_LOAD
M0:M8, SSC_CTL0,
Input Low Voltage SSC_CTL1, MR,
TEST_I/O, nP_LOAD
M7, M8, SSC_CTL0,
SSC_CTL1, TEST_IO
Input High Current
M0:M6,
nP_LOAD, MR
M7, M8, SSC_CTL0,
SSC_CTL1, TEST_IO
Input Low Current
M0:M6,
nP_LOAD, MR
Test Conditions
3.135V
≤
V
CC
≤
3.465V
3.135V
≤
V
CC
≤
3.465V
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
-150
-5
Minimum Typical
2
Maximum
V
CC
+ 0.3
Units
V
V
IL
-0.3
0.8
5
150
V
µA
µA
µA
µA
I
IH
I
IL
T
ABLE
4C. LVPECL DC C
HARACTERISTICS
,
V
CC
= V
CCA
= V
CCO
= 3.3V±5%, T
A
= 0°C
TO
85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CCO
- 1.4
V
CCO
- 2.0
600
700
Typical
Maximum
V
CCO
- 1.0
V
CCO
- 1.7
850
Units
V
V
mV
NOTE 1: Output terminated with 50Ω to V
CCO
- 2V. See Parameter Measurement Section, 3.3V Output Load Test Circuit.
ICS8431EM REVISION D MAY 14, 2014
5
©2014 Integrated Device Technology, Inc.
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