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TMX320C6412GNZ

Description
64-BIT, 75.19 MHz, OTHER DSP, PBGA548, 27 X 27 MM, 1 MM PITCH, PLASTIC, BGA-548
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size3MB,163 Pages
ManufacturerRochester Electronics
Websitehttps://www.rocelec.com/
Download Datasheet Parametric View All

TMX320C6412GNZ Overview

64-BIT, 75.19 MHz, OTHER DSP, PBGA548, 27 X 27 MM, 1 MM PITCH, PLASTIC, BGA-548

TMX320C6412GNZ Parametric

Parameter NameAttribute value
MakerRochester Electronics
Parts packaging codeBGA
package instructionBGA,
Contacts548
Reach Compliance Codeunknown
Other featuresALSO REQUIRES 3.3V SUPPLY
Address bus width23
barrel shifterNO
boundary scanYES
maximum clock frequency75.19 MHz
External data bus width64
FormatFIXED POINT
Internal bus architectureMULTIPLE
JESD-30 codeS-PBGA-B548
length27 mm
low power modeYES
Number of terminals548
Package body materialPLASTIC/EPOXY
encapsulated codeBGA
Package shapeSQUARE
Package formGRID ARRAY
Certification statusCOMMERCIAL
Maximum seat height2.8 mm
Maximum supply voltage1.44 V
Minimum supply voltage1.36 V
Nominal supply voltage1.4 V
surface mountYES
technologyCMOS
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM
width27 mm
uPs/uCs/peripheral integrated circuit typeDIGITAL SIGNAL PROCESSOR, OTHER

TMX320C6412GNZ Preview

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TMS320C6412 Fixed-Point Digital
Signal Processor
Data Manual
Literature Number: SPRS219G
April 2003
Revised October 2005
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
This page intentionally left blank
Revision History
Revision History
This data manual revision history highlights the technical changes made to the SPRS219F device-specific data
sheet to make it an SPRS219G revision.
Scope:
Applicable updates to the C64x device family, specifically relating to the TMS320C6412 device, have
been incorporated.
Added the device-specific information supporting the
TMS320C6412
silicon revision 2.0, 1.2, 1.1, and 1.0
devices, which are now in the production data (PD) stage of development.
PAGE(s)
NO.
Global
49
Clarified PCI66 as active low (PCI66)
Device Configurations, Configurations at Reset, Device Configuration at Device Reset section:
C6412 Device Configuration Pins (TOUT1/LENDIAN, AEA[22:19], GP0[3]/PCIEEAI, GP0[8]/PCI66, HD5/AD5, PCI_EN, and
TOUT0/MAC_EN) table:
Updated the Functional Description for Bootmode [1:0] for AEA22:21 Configuration Pin
from
“11
EMIFA boot”
to
“11
EMIFA 8−bit ROM boot”
Device Configurations, Device Status Register Description section:
Device Status (DEVSTAT) Register Selection Bit Descriptions table:
Updated Description for Bits 3 and 2, Bootmode1 and Bootmode0 Name
from
“11
EMIFA boot”
to
“11
EMIFA 8−bit ROM
boot”
Terminal Functions table:
Reset, Interrupts, and General−Purpose Input/Output section:
Updated Description for NMI pin
CLKOUT6/GPO[2]: changed “IPD” to “IPU”
CLKOUT4/GPO[1]: changed “IPD” to “IPU”
Terminal Functions table:
EMIFA (64−BIT)
ADDRESS section:
Updated the Description for Boot Configuration for AEA22:3 Signal Name
from
“11
EMIFA boot”
to
“11
EMIFA 8−bit ROM
boot”
Device Support, Device and Development-Support Tool Nomenclature:
Updated the TMS320C64x DSP Device Nomenclature (Including the C6412 Device) figure
IEEE 1149.1 JTAG Compatibility Statement section:
Updated/added paragraphs for clarity
Recommended Operating Conditions:
V
OS,
Maximum voltage during overshoot row
Deleted
−1.0
from MIN
Added V
US,
Maximum voltage during undershoot row
104
Parameter Information, Signal Transition Rates section:
Added AC transient Rise/Fall Time Specifications section, which includes the following figures:
Added AC Transient Specification Rise Time figure
Added AC Transient Specification Fall Time figure
Parameter Information, Input and Output Clocks section:
Switching Characteristics Over Recommended Operating Conditions for AECLKOUT2 for the EMIFA Module table:
Updated Parameter No. 5
from
“t
d(EKIH-EKO2L)”
to
“t
d(EKIL-EKO2L)”
Updated Parameter No. 5
from
“Delay time, AECLKIN
high
to AECLKOUT2 low”
to
“Delay time, AECLKIN
low
to AECLK-
OUT2 low”
ADDS/CHANGES/DELETES
54
61
66
84
99
101
110
April 2003
Revised October 2005
SPRS219G
3
Revision History
PAGE(s)
NO.
Asynchronous Memory Timing section:
111
Timing Requirements for Asynchronous Memory Cycles for EMIFA Module table:
Updated Parameter No. 7, t
h(EKO1H-ARDY)
MIN
from
“2.0” to “2.5”
Switching Characteristics Over Recommended Operating Conditions for Asynchronous Memory Cycles for EMIFA Module
table:
Updated Parameter No. 1, t
osu(SELV-AREL)
MIN
from
“RS*E
1.5”
to
“RS*E
1.8”
Updated Parameter No. 8, t
osu(SELV-AWEL)
MIN
from
“WS*E
1.7”
to
“WS*E
2.0”
Programmable Synchronous Interface Timing section:
114
Timing Requirements for Programmable Synchronous Interface Cycles for EMIFA Module table:
Updated Parameter No. 7, t
h(EKOxH-EDV)
MIN
from
“1.5”
to
“1.8” for
−500
device speed
Switching Characteristics Over Recommended Operating Conditions for Programmable Synchronous Interface Cycles for
EMIFA Module table:
Updated all delay times MIN for
−500, −600
and
−720
device speeds
from
“1.3”
to “1.1”
Synchronous DRAM Timing section:
Timing Requirements for Asynchronous Memory Cycles for EMIFA Module table:
Updated Parameter No. 7, t
h(EKO1H-ARDY)
MIN
from
“2.5”
to
“2.8” for
−500
device speed
Updated Parameter No. 7, t
h(EKO1H-ARDY)
MIN
from
“1.8”
to
“2.1” for
−600
and
−720
device speeds
Multichannel Buffered Serial Port (McBSP) Timing section:
Switching Characteristics Over Recommended Operating Conditions for McBSP table:
Updated Parameter No. 12, t
dis(CKXH-DXHZ))
MIN
from
“2.0”
to
“−2.1”
Updated Parameter No. 13, td
(CKXH-DXV)
MIN
from
“2.0 + D1”
to
“−2.1 + D1”
Ethernet Media Access Controller (EMAC) Timing section:
Timing Requirements for EMAC MII Receive 10/100 Mbit/s table:
Deleted paragraph
Switching Characteristics Over Recommended Operating Conditions for EMAC
MII Transmit 10/100 Mbit/s table:
Deleted paragraph
ADDS/CHANGES/DELETES
111
114
118
140
148
4
SPRS219G
April 2003
Revised October 2005
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