QL5840-33APS484I datasheet, PDF

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QL5840-33APS484I: DescriptionPCI Bus Controller, CMOS, PBGA484, 23 X 23 MM, 2.13 MM HEIGHT, 1 MM PITCH, PLASTIC, MS-034AAJ-1, BGA-484; CategoryThe embedded processor and controller Microcontrollers and processors; File Size1MB，80 Pages; ManufacturerQuickLogic Corporation; Websitehttps://www.quicklogic.com

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QL5840-33APS484I Overview

PCI Bus Controller, CMOS, PBGA484, 23 X 23 MM, 2.13 MM HEIGHT, 1 MM PITCH, PLASTIC, MS-034AAJ-1, BGA-484

QL5840-33APS484I Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	QuickLogic Corporation
Parts packaging code	BGA
package instruction	BGA, BGA484,22X22,40
Contacts	484
Reach Compliance Code	compliant
ECCN code	3A991.A.2
Address bus width	32
maximum clock frequency	33 MHz
Maximum data transfer rate	264 MBps
External data bus width	32
JESD-30 code	S-PBGA-B484
JESD-609 code	e0
length	23 mm
Humidity sensitivity level	3
Number of terminals	484
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA484,22X22,40
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	1.8,3.3 V
Certification status	Not Qualified
Maximum seat height	2.34 mm
Maximum slew rate	3 mA
Maximum supply voltage	1.89 V
Minimum supply voltage	1.71 V
Nominal supply voltage	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	23 mm
uPs/uCs/peripheral integrated circuit type	BUS CONTROLLER, PCI

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QL58x0 Enhanced QuickPCI®

Target Family Data

Sheet

• • • • • •

33/66

MHz/32-bit PCI Target with Embedded Programmable

Device Highlights

High Performance PCI Controller

• 33/66 MHz 32-bit PCI Target

• Zero-wait state PCI Target provides up to

264 MBps transfer rates

• Target interface supports retry, disconnect

with/without data transfer, and target abort

• Fully programmable back-end interface

• Independent PCI bus (33/66 MHz) and local bus

(up to 160 MHz) clocks

• Fully customizable PCI Configuration Space

• Configurable FIFOs with depths up to 256 words

• Reference design with driver code

(Win 95/98/2000/NT 4.0) available

• PCI v2.3 compliant

• Supports Type 0 configuration cycles

• 3.3 V PCI signaling

• 1.8 V supply voltage

• 484-ball PBGA, 280-ball LFBGA, 208-pin PQFP,

196-ball TFBGA, and 144-pin TQFP packages

• Unlimited/Continuous Burst Transfers supported

Figure 1: QL58x0 Block Diagram

Logic, Embedded Computational Units, and Dual Port

SRAM

Extendable PCI Functionality

• Support for Configuration Space from

40 to 0

3FF

• PCI v2.3 Power Management Spec. compatible

• PCI v2.3 Vital Product Data (VPD) configuration

support

Flexible Programmable Logic

• Up to 1,478 logic cells

• Up to 50,688 RAM bits

• Up to 264 I/O pins

• All back-end interface and glue-logic can be

implemented on chip

• Two 32-bit busses interface between the PCI

Controller and the Programmable Logic

• Up to twenty-two 2,304 bit dual-port high

performance SRAM blocks

• Up to 3,748 flip-flops available

PCI Bus 33/66 MHz/32 bits (data and

address)

High Speed

Data Path

PCI Controller

32-bit Interface

Programmable

Logic

Target

Controller

264 User I/O

160 MHz

FIFOs

PCI Bus

High Speed

Logic Cells

Config.

Space

www.quicklogic.com

•

QL58x0 Enhanced QuickPCI® Target Family Data Sheet Rev. L

Architecture Overview

The QL58x0 device family of QuickPCI Embedded Standard Products (ESPs) provides a complete and

customizable PCI interface solution combined with programmable logic. Since the QL58x0 devices provide

optimized pre-verified PCI cores, the burden of PCI timing closure and PCI protocol compliance has been

eliminated and allows for the maximum 32-bit PCI bus bandwidth (264 MBps).

The programmable logic portion of this family contains up to 1,478 QuickLogic Logic Cells and up to 22

QuickLogic Dual-Port RAM Blocks. These configurable RAM blocks can be configured in many width/depth

combinations. They can also be combined with logic cells to form FIFOs, or be initialized via Serial EEPROM

on power-up and used as ROMs.

The QL58x0 device meets PCI 2.3 electrical and timing specifications and has been fully hardware-tested. The

QL58x0 device features 1.8 V operation with multi-volt compatible I/Os. The device can easily operate in

3.3 V embedded systems and is fully compatible with 3.3 V applications.

PCI Controller

The PCI Controller is a 33/66 MHz 32-bit PCI 2.3 compliant Target Controller capable of infinite length

Target Write and Read transactions at zero wait states (264 MBps).

The Target interface offers full PCI Configuration Space and flexible target addressing. It supports zero-wait-

state target Write and Read operations. It also supports retry, disconnect with/without data transfer, and target

abort requested by the back end. Any number of 32-bit BARs may be configured as either memory or I/O

space. All required and optional PCI 2.3 Configuration Space registers can be implemented within the

programmable region of the device. A reference design of a Target Configuration Space and Addressing

module is available and is included in the QuickWorks® design software.

The interface ports are designed for target transactions. The Target Configuration Space and Address

Decoding are done in the programmable logic region of the device. These functions are not timing critical, so

leaving these elements in the programmable region allows the greatest degree of flexibility to the designer.

Table 1

shows several commonly implemented IP cores in the programmable logic portion of the Target

Controller device. Their respective logic cell utilization and performance information are shown for easy

reference. Notice that the Configuration Space and Address Decoding core is labelled as an essential IP core.

This IP block is necessary for the Target Controller to be fully functional. The optional IP cores are common

interface IP cores made available so that designers may implement according to their design requirements.

These optional IP cores do not affect the functionality of the Target Controller.

•

www.quicklogic.com

•

QL58x0 Enhanced QuickPCI® Target Family Data Sheet Rev. L

PCI Target Interface

Table 2: PCI Target Interface

Signal

I/O

Description

Target address, and target Write data.

During all target accesses, the address is

presented on Usr_Addr_WrData[31:0]; at the same time, Usr_Adr_Valid is active.

During target Write transactions, this port also presents valid Write data to the PCI

configuration space or user logic when Usr_Adr_Inc is active.

PCI command and byte enables.

During target accesses, the PCI command is

presented on Usr_CBE[3:0]; at the same time, Usr_Adr_Valid is active. This port also

presents active-low byte enables to the PCI configuration space or user logic.

Indicates the beginning of a PCI transaction, and that a target address is valid on

Usr_Addr_WrData[31:0] and the PCI command is valid on Usr_CBE[3:0]. When this

signal is active, the target address must be latched and decoded to determine if this

address belongs to the device's memory or I/O space. Also, the PCI command must

be decoded to determine the type of PCI transaction. On subsequent clocks of a target

access, this signal is low, indicating that address is NOT present on

Usr_Addr_WrData[31:0].

Indicates that the target address should be incremented, because the previous data

transfer has completed. During burst target accesses, the target address is only

presented to the back-end logic at the beginning of the transaction (when

Usr_Adr_Valid is active), and must therefore be latched and incremented by four for

subsequent data transfers. Note that during target Write transactions, Usr_Adr_Inc

indicates valid data on Usr_Addr_WrData[31:0] that must be accepted by the backend

logic (regardless of the state of Usr_Rdy). During Read transactions, Usr_Adr_Inc

signals to the backend that the PCI core has presented the read data on the PCI bus

(TRDYN asserted).

This signal should be the combinatorial decode of the “user read” command from

Usr_CBE[3:0]. This command may be mapped from any of the PCI Read commands,

such as Memory Read, Memory Read Line, Memory Read Multiple, I/O Read, etc. It

is internally gated with Usr_Adr_Valid.

This signal should be the combinatorial decode of the “user write” command from

Usr_CBE[3:0]. This command may be mapped from any of the PCI Write commands,

such as Memory Write or I/O Write. It is internally gated with Usr_Adr_Valid.

This signal should be driven active when the address on Usr_Addr_WrData[31:0] has

been decoded and determined to be within the address space of the device.

Usr_Addr_WrData[31:0] must be compared to each of the valid Base Address

Registers in the PCI configuration space. Also, this signal must be gated by the

Memory Access Enable or I/O Access Enable registers in the PCI configuration space

(Command Register bits 1 or 0 at offset 04h). Internally gated with Usr_Adr_Valid.

This signal is active throughout a “user write” transaction, which has been decoded by

Usr_WrDecode at the beginning of the transaction. The Write strobe for individual

DWORDs of data (on Usr_Addr_WrData[31:0]) during a user Write transaction should

be generated by logically ANDing this signal with Usr_Adr_Inc.

This signal is active throughout a “configuration write” transaction. The Write strobe

for individual DWORDs of data (on Usr_Addr_WrData[31:0]) during a configuration

Write transaction should be generated by logically ANDing this signal with

Usr_Adr_Inc.

Data from the PCI configuration registers, required to be presented during PCI

configuration reads.

Usr_Addr_WrData[31:0]

Usr_CBE[3:0]

Usr_Adr_Valid

Usr_Adr_Inc

Usr_RdDecode

Usr_WrDecode

Usr_Select

Usr_Write

Cfg_Write

Cfg_RdData[31:0]

www.quicklogic.com

•

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