MB9D560 Series
32-bit Microcontroller
Traveo
TM
Family
MB9D560 series has Cypress 32-bit microcontrollers for automobile motor control. They use the ARM
®
Cortex-R5 MPCore
TM
CPU
that is compatible with the ARM family.
Notes:
• ARM, Cortex, Thumb are the registered trademarks of ARM Limited in the EU and other countries.
• MPCore, CoreSight are the trademarks of ARM Limited in the EU and other countries.
Features
Technology
CMOS 90nm technology
CPU
ARM Cortex
®
-R5F
32-bit ARM architecture
2-instruction issuance super scalar
8-stage pipeline
ARMv7 / Thumb
®
-2 instruction set
Floating-Point Unit (FPU)
Double
Debugging
ARM CoreSight
TM
Technology
Each
CPU embedded Embedded Trace Macro (ETM),
trace support of CPU operation
Debugging interface
(5 pin )
Support clock : maximum 20 MHz
JTAG
Debugging security support
128-bit
security key (Device security key)
Wakeup function on JTAG
Operation mode
User mode
Normal
precision
Memory protection Unit (MPU)
16
area
error correction, 2-bit error detection ECC (SEC-DED)
mode (internal memory activation)
ECC support for the TCM port
1-bit
Serial writer mode
Clock control
Internal clock source
Fast-CR
Slow-CR
TCM port
2
TCM ports
ATCM port
BTCM 2 ports (B0TCM, B1TCM)
VIC port
Low
oscillation (8 MHz)
oscillation (100 kHz)
External oscillation input
Main
clock input
PLL (Multiplying clock of main oscillation )
latency interrupt
Embedded PLL
Main
AXI master interface
interface (instruction / data access)
32-bit AXI interface (I/O access)
64-bit AXI
Oscillator stabilized timer
oscillator stabilized timer for all clock source
independently
After a lapse of oscillator stabilized time, it is able to use
source clock timer (Except PLL for FlexRay/RDC)
Support
AXI slave interface
64-bit AXI
interface (accessible to TCM port)
CPU configuration
2
CPUs (AMP operation)
200 MHz
Operating frequency
Maximum
Trace with ETM-R5
Cypress Semiconductor Corporation
Document Number: 002-05679 Rev.*A
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised March 22, 2016
MB9D560 Series
Reset control
Reset level
Hardware
Watchdog timer (WDT)
Watchdog timer embedded
Hardware
reset (system initialization)
Software reset (programing initialization)
watchdog timer
Software watchdog timer
Reset factor (Hardware reset )
Power-on
Hardware watchdog timer
unit per system
32-bit watchdog timer with window function
Clock source: fast-CR or slow-CR
Set by boot program (BootROM maker)
Not set by user program
1
reset (PONR), external reset input (RSTX,
NMIX+RSTX), clock stop waiting with time-out reset,
low-voltage detection reset (internal low-voltage detection
reset, 5V external low-voltage detection reset ), watchdog
reset (hardware watchdog reset, software watchdog reset ),
clock supervisor reset (main clock monitor, PLL clock
monitor), software trigger hardware reset , profile error
reset
reset
Software watchdog timer
unit per CPU
32-bit watchdog timer with window function
Clock source: fast-CR, slow-CR, main clock
One time set on user program (not set again)
1
Reset factor (software reset )
Software
Low power consumption control
Device state
RUN
Low-voltage detection (LVD)
Select voltage monitor
low-voltage detection (5V power line monitor):
3.9V, 4.1V, 4.3V
Internal low-voltage detection (1.2V power line monitor):
0.9V
External
(Run State, CPU is operation status)
PSS (Power Saving State, CPU wait event from WFI)
Setting parameter of each devise state
Clock
(clock source enable, clock source selection, clock
divider, clock domain enable)
Clock monitor
Low-voltage detection
Internal low-voltage detection: always valid
External low-voltage detection: valid/invalid set
External low-voltage detection: set threshold voltage
independently on RUN / PSS
Memory protection unit (MPU)
Memory protection as master except processor
Target master
DMA controller
Output when low-voltage detection
External
Internal
low-voltage detection: reset or NMI
low-voltage detection: reset
8 area
NMI generation when violation detection
Timing protection unit (TPU)
TPU 1 unit as CPU 1 unit
24-bit timer x 8 channels per unit
Support execution time protection, locking time protection,
inter-arrival time protection, deadline protection
Main Flash memory (TCFLASH)
Cortex-R5F ATCM connection
1
Main Flash memory as CPU 1 unit
HPM connection with 64-bit AXI
Flash memory configuration
Interleave
with 64-bit Flash 2 units
2 address areas
(read only)
AXI (read / write)
TCM
Support normal mode and over flow mode
Prescaler of each channels
Timer
clock divider (1/1 to 1/64)
clock divider (1/1, 1/2, 1/4, 1/16)
ECC support (SEC-DED)
Parallel programming support
Flash security
Work Flash memory (WorkFLASH)
2 Work Flash memories
1
Independent prescaler of each channels
Timer
Clock supervisor (CSV)
Monitor target clock
Main
oscillation input , main PLL output
of frequency range
Work Flash memory as CPU 1 unit
Monitor method
Monitor
ECC support (SEC-DED)
Parallel programming support
Flash security
Page 2 of 91
Operation after error detection
Reset
or NMI
Document Number: 002-05679 Rev.*A
MB9D560 Series
Main SRAM (TCRAM)
BTCM connection of Cortex-R5F
main SRAM as CPU 1 unit
Interleave with 2 ports of B0TCM and B1TCM
1
Exclusion access memory (EAM)
Small size memory to support exclusion control on exclusion
access instruction
Use for semaphore
Size: 48 byte
Bit-band unit (BBU)
The bit operation of specified register bit on Bit band area, it
is mapping 1 bit of bit band area to support bit band alias
area for 1 byte. The target of bit band access is specified
register bit on I/O area
ECC support (SEC-DED)
BootROM
Size: 16K byte
Boot operation support
Serial writer program support
DMA controller (DMAC)
16 channels
Transfer mode
Block
CRC
Output to register of CRC code according real time writing to
input register
transfer, Burst transfer
increment
Dynamic, Round robin
Addressing mode
Fixed,
Base timer
16-bit timer
of four PWM/PPG/reload/PWC timer functions can be
selected and used.
A 32-bit timer can be used in 2 channels of cascade mode
as reload/PWC timer.
Any
Priority between channels
Fixed,
Interrupt control (IRC)
Support normal interrupt (IRQ) and non-maskable interrupt
(NMI)
16-bit free-run timer (FRT)
16 bit up/down counter (2 channels for motor control only)
32-bit free-run timer
32 bit up/down counter
16-bit input capture (ICU)
Input capture
16-bit
Normal interrupt (IRQ)
Use
Interrupt Request (IRQ) of Cortex-R5F
512 channels
32 level for priority
Support low latency interrupt response from VIC port of
Cortex-R5F
Non-maskable interrupt (NMI)
fast interrupt request (FIQ) of Cortex-R5F
32 channels
16 level for priority
Use
Support software interrupt generation
External interrupt (EXT-IRQ)
Input
interrupt (IRQ): 8 input
Non-maskable interrupt (NMI): 1 input
Normal
capture register that detects rise edge, Fall edge,
both edge
Generate interrupt request after latch of counter number of
16 bit
Free-run timer with edge detection of pin input
32-bit input capture
Input capture
capture register that detects rise edge, fall edge,
both edge
Generate interrupt request after latch of counter number of
32 bit
Free-run timer with edge detection of pin input
32-bit
Detection method
H
level , L level , rise edge, fall edge, both edge
LIN sync break/sync field relation is following.
capture ch.0
Multi-function serial interface ch.0
Input capture ch.1
Multi-function serial interface ch.1
Input capture ch.2
Multi-function serial interface ch.2
Input capture ch.3
Multi-function serial interface ch.3
Input capture ch.4
Multi-function serial interface ch.4
Input
Inter-processor communications unit (IPCU)
Mailbox function
communication for CPU core communication by 8
Mailbox
Support of interrupt between CPU core
Data
16-bit output compare (OCU)
Output interrupt signal when compare with 16-bit free-run
timer
Document Number: 002-05679 Rev.*A
Page 3 of 91
MB9D560 Series
Waveform generator (WFG)
Generate variable output
time output
16-bit PPG waveform output
PPG uses 16-bit PPG timer of base timer
The relation is following
WFG(ch.0 to ch.5)
• Base timer ch.0
PPG0
• Base timer ch.2
PPG2
• Base timer ch.4
PPG4
WFG(ch.6 to ch.11)
• Base timer ch.6
PPG6
• Base timer ch.8
PPG8
• Base timer ch.10
PPG10
Non overlap three-phase waveform output (inverter
control)
DC chopper waveform output
Real
CAN interface
The CAN is based on the CAN protocol ver. 2.0A/B
64 message buffers x 3 channels
An identification mask is applied to each message object
Up to 1Mbps support
Clock support CAN prescaler
CAN wakeup functions
FlexRay controller
Supports FlexRay protocol specification v2.1
Maximum 128 message buffers
8K Byte message RAM
Variable length of message buffers
Each message buffer can be allocated as a part of reception
buffer, transmission buffer or reception FIFO
Dead time timer function
GATE function
DTTI function
A/D converter (ADC)
12-bit resolution A/D converter: 1 unit (32 channels)
Sampling analog value from input port of 32 channels
Conversion time: 1
s
External trigger activation (ADTG)
Activation from internal timer (base timer)
4ch sample-hold A/D converter
12 bit resolution A/D converter: 2 units (8 channels )
Multi-function serial interface (MFS)
UART / CSIO / LIN interface (v2.1) communication available
by selecting the function
Host access to the message buffer via input and output
buffers
Filtering for slot counter, cycle counter and channels
Maskable interrupts are supported
R/D converter (RDC)
Connect to resolver interface
D/A converter (DAC)
10-bit resolution
Motor vector operation accelerator (MVA)
Assist for three-phase current normalizing, three-phase to
two-phase DC conversion / two-phase to three- phase AC
conversion, angler calculation, PID control calculation.
Error detection in processing (overflow/under flow/non
normalizing error of FLOP)
Transmission FIFO: 64 Byte, reception FIFO: 64 Byte
Reception interrupt factor (3 types)
error detection (parity, over run, frame error)
Reception to FIFO for data of setting value
Reception data under setting value in FIFO, idle term
detection of over 8 clocks with baud rate clock
Reception
Amplitude diagnosis /angle diagnosis function of R/D
converter
Error current diagnosis function
Key code
Key code supports
of General-purpose I/O (GPIO) register
Port pin configuration (PPC) register
Analog input control register (ADER)
4ch ADC analog input control register (ADER4CH_1,
ADER4CH_0)
Analog output control register (DAC00_DAER,
DAC01_DAER)
A part
Transmission interrupt factor (2 types)
transmission operation
Transmission FIFO empty (contain transmission operation)
No
SPI (serial peripheral interface) support
LIN protocol revision 2.1 support
Up/Down counter (UDC)
8/16-bit up/down counter (2 channels uses for R/D converter)
Document Number: 002-05679 Rev.*A
Page 4 of 91
MB9D560 Series
Contents
1. Product Lineup .................................................................................................................................................................. 6
2. Pin Assignment ................................................................................................................................................................. 7
3. Pin Description ................................................................................................................................................................ 11
4. I/O Circuit Type ............................................................................................................................................................... 25
5. Handling Precautions ..................................................................................................................................................... 28
5.1
Precautions for Product Design ................................................................................................................................... 28
5.2
Precautions for Package Mounting .............................................................................................................................. 29
5.3
Precautions for Use Environment ................................................................................................................................ 30
6. Handling Devices ............................................................................................................................................................ 31
7. Block Diagram ................................................................................................................................................................. 33
8. Memory Map .................................................................................................................................................................... 35
9. I/O Map ............................................................................................................................................................................. 38
10. Pin Statuses in CPU Status ............................................................................................................................................ 42
11. Electrical Characteristics ............................................................................................................................................... 44
11.1 Absolute Maximum Ratings ......................................................................................................................................... 44
11.2 Recommended Operating Conditions ......................................................................................................................... 46
11.3 DC Characteristics ...................................................................................................................................................... 47
11.4 AC Characteristics ....................................................................................................................................................... 54
11.4.1 Source Clock Timing .................................................................................................................................................... 54
11.4.2 Internal Clock Timing ................................................................................................................................................... 55
11.4.3 Reset Input ................................................................................................................................................................... 58
11.4.4 Power-on Conditions .................................................................................................................................................... 59
11.4.5 Multi-Function Serial Interface ..................................................................................................................................... 60
11.4.6 Timer Input Timing ....................................................................................................................................................... 77
11.4.7 Trigger Input Timing ..................................................................................................................................................... 78
11.4.8 NMI Input Timing .......................................................................................................................................................... 79
11.4.9 External Low-Voltage Detection ................................................................................................................................... 80
11.4.10 Internal Low-Voltage Detection................................................................................................................................. 80
11.5 A/D Converter .............................................................................................................................................................. 81
11.5.1 Electrical Characteristics .............................................................................................................................................. 81
11.5.2 Notes on Using A/D Converter ..................................................................................................................................... 81
11.6 4 Channels Same Time Sampling A/D Converter ....................................................................................................... 82
11.6.1 Electrical Characteristics .............................................................................................................................................. 82
11.6.2 Notes on Using A/D converter ...................................................................................................................................... 82
11.6.3 Definition of Terms ....................................................................................................................................................... 83
11.7 Flash Memory .............................................................................................................................................................. 84
11.8 R/D Converter ............................................................................................................................................................. 85
12. Ordering Information ...................................................................................................................................................... 86
13. Part Number Option ........................................................................................................................................................ 86
14. Package Dimensions ...................................................................................................................................................... 87
15. Major Changes ................................................................................................................................................................ 89
Document History ................................................................................................................................................................. 90
Document Number: 002-05679 Rev.*A
Page 5 of 91
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