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ZNBR4000Q16

Description
Analog Circuit, 1 Func, PDSO16, QSOP-16
CategoryAnalog mixed-signal IC    The signal circuit   
File Size184KB,10 Pages
ManufacturerDiodes Incorporated
Download Datasheet Parametric Compare View All

ZNBR4000Q16 Overview

Analog Circuit, 1 Func, PDSO16, QSOP-16

ZNBR4000Q16 Parametric

Parameter NameAttribute value
MakerDiodes Incorporated
Parts packaging codeSOIC
package instructionSSOP,
Contacts16
Reach Compliance Codeunknown
Analog Integrated Circuits - Other TypesANALOG CIRCUIT
JESD-30 codeR-PDSO-G16
JESD-609 codee3
length4.9 mm
Humidity sensitivity level1
Number of functions1
Number of terminals16
Maximum operating temperature70 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
Certification statusNot Qualified
Maximum seat height1.75 mm
Maximum supply voltage (Vsup)12 V
Minimum supply voltage (Vsup)3.5 V
Nominal supply voltage (Vsup)4 V
surface mountYES
Temperature levelOTHER
Terminal surfaceMATTE TIN
Terminal formGULL WING
Terminal pitch0.635 mm
Terminal locationDUAL
Maximum time at peak reflow temperature40
width3.9116 mm
FET BIAS CONTROLLER
DRAFT ISSUE A - DECEMBER 2000
DEVICE DESCRIPTION
The ZNBR series of devices are designed to
meet the bias requirements of GaAs and
HEMT FETs commonly used in satellite
receiver LNBs, PMR, cellular telephones etc.
with a minimum of external components
and a V
CC
of 3-6V for improved efficiency.
With the addition of two capacitors and
resistors the devices provide drain voltage
and current control for a number of external
grounded source FETs, generating the
regulated negative rail required for FET gate
biasing whilst operating from a single
supply. This negative bias, at -3 volts, can
also be used to supply other external
circuits.
The ZNBR4000/1 and ZNBR6000/1 contain
four and six bias stages respectively. In
setting drain current the ZNBR4000/1 two
resistors allows individual FET pair control
to different levels, the ZNBR6000/1 two
resistors split control between two and four
FETs. This allows the operating current of
input FETs to be adjusted to minimise noise,
whilst the following FET stages can
separately be adjusted for maximum gain.
The series also offers the choice of drain
v o lta g e t o b e s e t f or t he F E Ts, the
ZNBR4000/6000 gives 2.2 volts drain whilst
the ZNBR4001/6001 gives 2 volts.
ZNBR4000 ZNBR4001
ZNBR6000 ZNBR6001
These devices are unconditionally stable
over the full working temperature with the
FETs in place, subject to the inclusion of the
recommended gate and drain capacitors.
These ensure RF stability and minimal
injected noise.
It is possible to use less than the devices full
complement of FET bias controls, unused
drain and gate connections can be left open
circuit without affecting operation of the
remaining bias circuits.
In order to protect the external FETs the
circuits have been designed to ensure that,
under any conditions including power
up/down transients, the gate drive from the
bias circuits cannot exceed the range -2.5V
to 0.7V. Furthermore if the negative rail
experiences a fault condition, such as
overload or short circuit, the drain supply to
the FETs will shut down avoiding excessive
current flow.
The ZNBR4000/1 and ZNBR6000/1 are
available in QSOP16 and 20 pin packages
respectively for the minimum in devices size.
Device operating temperature is -40 to 70°C
to suit a wide range of environmental
conditions.
FEATURES
APPLICATIONS
V
CC
of 3-6V for improved efficiency
Provides bias for GaAs and HEMT FETs
Drives up to four or six FETs
Dynamic FET protection
Drain current set by external resistor
Regulated negative rail generator
requires only 2 external capacitors
Choice in drain voltage
Wide supply voltage range
QSOP surface mount package
Satellite receiver LNBs
Private mobile radio (PMR)
Cellular telephones
1

ZNBR4000Q16 Related Products

ZNBR4000Q16 ZNBR6001Q20 ZNBR6000Q20
Description Analog Circuit, 1 Func, PDSO16, QSOP-16 Analog Circuit, 1 Func, PDSO20, QSOP-20 Analog Circuit, 1 Func, PDSO20, QSOP-20
Maker Diodes Incorporated Diodes Incorporated Diodes Incorporated
Parts packaging code SOIC QSOP QSOP
package instruction SSOP, SSOP, SSOP,
Contacts 16 20 20
Reach Compliance Code unknown unknown unknown
Analog Integrated Circuits - Other Types ANALOG CIRCUIT ANALOG CIRCUIT ANALOG CIRCUIT
JESD-30 code R-PDSO-G16 R-PDSO-G20 R-PDSO-G20
JESD-609 code e3 e3 e3
length 4.9 mm 8.65 mm 8.65 mm
Humidity sensitivity level 1 1 1
Number of functions 1 1 1
Number of terminals 16 20 20
Maximum operating temperature 70 °C 70 °C 70 °C
Minimum operating temperature -40 °C -40 °C -40 °C
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code SSOP SSOP SSOP
Package shape RECTANGULAR RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Celsius) 260 260 260
Certification status Not Qualified Not Qualified Not Qualified
Maximum seat height 1.75 mm 1.75 mm 1.75 mm
Maximum supply voltage (Vsup) 12 V 12 V 12 V
Minimum supply voltage (Vsup) 3.5 V 3 V 3.5 V
Nominal supply voltage (Vsup) 4 V 4 V 4 V
surface mount YES YES YES
Temperature level OTHER OTHER OTHER
Terminal surface MATTE TIN MATTE TIN MATTE TIN
Terminal form GULL WING GULL WING GULL WING
Terminal pitch 0.635 mm 0.635 mm 0.635 mm
Terminal location DUAL DUAL DUAL
Maximum time at peak reflow temperature 40 40 40
width 3.9116 mm 3.9116 mm 3.9116 mm
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