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7016S20GG8

Description
Dual-Port SRAM, 16KX9, 20ns, CMOS, CPGA68, 1.180 X 1.180 INCH, 0.160 INCH HEIGHT, GREEN, CERAMIC, PGA-68
Categorystorage    storage   
File Size346KB,21 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

7016S20GG8 Overview

Dual-Port SRAM, 16KX9, 20ns, CMOS, CPGA68, 1.180 X 1.180 INCH, 0.160 INCH HEIGHT, GREEN, CERAMIC, PGA-68

7016S20GG8 Parametric

Parameter NameAttribute value
MakerIDT (Integrated Device Technology)
package instructionPGA,
Reach Compliance Codecompliant
Maximum access time20 ns
JESD-30 codeS-CPGA-P68
JESD-609 codee3
length29.464 mm
memory density147456 bit
Memory IC TypeDUAL-PORT SRAM
memory width9
Number of functions1
Number of terminals68
word count16384 words
character code16000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize16KX9
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codePGA
Package shapeSQUARE
Package formGRID ARRAY
Parallel/SerialPARALLEL
Maximum seat height5.207 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceMATTE TIN
Terminal formPIN/PEG
Terminal pitch2.54 mm
Terminal locationPERPENDICULAR
width29.464 mm
HIGH-SPEED
16K X 9 DUAL-PORT
STATIC RAM
Features
IDT7016S/L
True Dual-Ported memory cells which allow simulta-
neous reads of the same memory location
High-speed access
– Commercial:12/15/20/25/35ns (max.)
– Industrial: 20ns (max.)
– Military: 20/25/35ns (max.)
Low-power operation
– IDT7016S
Active: 750mW (typ.)
Standby: 5mW (typ.)
– IDT7016L
Active: 750mW (typ.)
Standby: 1mW (typ.)
IDT7016 easily expands data bus width to 18 bits or
more using the Master/Slave select when cascading
more than one device
M/S = V
IH
for
BUSY
output flag on Master
M/S = V
IL
for
BUSY
input on Slave
Busy and Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
TTL-compatible, single 5V (±10%) power supply
Available in ceramic 68-pin PGA, 68-pin PLCC, and an
80-pin TQFP
Industrial temperature range (–40°C to +85°C) is
available for selected speeds
Green parts available, see ordering information
Functional Block Diagram
OE
L
CE
L
R/W
L
OE
R
CE
R
R/W
R
I/O
0L
- I/O
8L
I/O
Control
BUSY
L
A
13L
A
0L
(1,2)
I/O
0R
-I/O
8R
I/O
Control
BUSY
R
Address
Decoder
14
(1,2)
MEMORY
ARRAY
14
Address
Decoder
A
13R
A
0R
CE
L
OE
L
R/W
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
OE
R
R/W
R
SEM
L
(2)
INT
L
NOTES:
1. In MASTER mode:
BUSY
is an output and is a push-pull driver
In SLAVE mode:
BUSY
is input.
2.
BUSY
outputs and
INT
outputs are non-tri-stated push-pull drivers.
M/S
3190 drw 01
SEM
R
(2)
INT
R
OCTOBER 2014
1
DSC 3190/11
©2014 Integrated Device Technology, Inc.
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