83023AMIT datasheet, PDF - EEWORLD Datasheet

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83023AMIT: DescriptionLow Skew Clock Driver, 83023 Series, 1 True Output(s), 0 Inverted Output(s), PDSO8, 3.80 X 4.80 MM, 1.47 MM HEIGHT, MS-012, SOIC-8; Categorylogic logic; File Size212KB，13 Pages; ManufacturerIDT (Integrated Device Technology)

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83023AMIT Overview

Low Skew Clock Driver, 83023 Series, 1 True Output(s), 0 Inverted Output(s), PDSO8, 3.80 X 4.80 MM, 1.47 MM HEIGHT, MS-012, SOIC-8

83023AMIT Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	SOIC
package instruction	3.80 X 4.80 MM, 1.47 MM HEIGHT, MS-012, SOIC-8
Contacts	8
Reach Compliance Code	not_compliant
ECCN code	EAR99
series	83023
Input adjustment	DIFFERENTIAL
JESD-30 code	R-PDSO-G8
JESD-609 code	e0
length	4.9 mm
Logic integrated circuit type	LOW SKEW CLOCK DRIVER
Humidity sensitivity level	1
Number of functions	2
Number of inverted outputs
Number of terminals	8
Actual output times	1
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP8,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	240
power supply	3.3 V
Prop。Delay @ Nom-Sup	2.4 ns
propagation delay (tpd)	2.4 ns
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.06 ns
Maximum seat height	1.75 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	3.9 mm

83023AMIT Preview

ICS83023I

UAL

, 1-

-1

IFFERENTIAL

-LVCMOS T

RANSLATOR

UFFER

ENERAL

ESCRIPTION

The ICS83023I is a dual, 1-to-1 Differential-to-LVCMOS

Translator/Fanout Buffer. The differential inputs can accept

most differential signal types (LVDS, LVHSTL, LVPECL, SSTL,

and HCSL) and translate into two single-ended LVCMOS

outputs. The small 8-lead SOIC footprint makes this device

ideal for use in applications with limited board space.

Features

•

Two LVCMOS / LVTTL outputs

•

Two differential CLKx, nCLKx input pairs

•

CLK, nCLK pairs can accept the following differential

input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL

•

Maximum output frequency: 350MHz (typical)

•

Output skew: 60ps (maximum)

•

Part-to-part skew: 500ps (maximum)

•

Additive phase jitter, RMS: 0.14ps (typical)

•

Small 8 lead SOIC package saves board space

•

3.3V operating supply

•

-40°C to 85°C ambient operating temperature

•

Available in both standard and lead-free RoHS-compliant

packages

LOCK

IAGRAM

CLK0

nCLK0

CLK1

nCLK1

SSIGNMENT

CLK0

nCLK0

nCLK1

CLK1

GND

ICS83023I

8-Lead SOIC

3.8mm x 4.8mm x 1.47mm package body

M Package

Top View

83023AMI

www.idt.com

REV. B JULY 29, 2010

ICS83023I

UAL

, 1-

-1

IFFERENTIAL

-LVCMOS T

RANSLATOR

UFFER

ABLE

1. P

ESCRIPTIONS

Number

Name

CLK0

nCLK0

nCLK1

CLK1

GND

Input

Power

Output

Power

Type

Pullup

Description

Inver ting differential clock input.

Power supply ground.

Single clock output. LVCMOS / LVTTL interface levels.

Positive supply pin.

Pulldown Non-inver ting differential clock input.

NOTE:

Pullup

and

Pulldown

refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

ABLE

2. P

HARACTERISTICS

Symbol

PULLUP

PULLDOWN

OUT

Parameter

Input Capacitance

Power Dissipation Capacitance

(per output)

Input Pullup Resistor

Input Pulldown Resistor

Output Impedance

Test Conditions

Minimum

Typical

= 3.6V

Maximum

Units

kΩ

83023AMI

www.idt.com

REV. B JULY 29, 2010

ICS83023I

UAL

, 1-

-1

IFFERENTIAL

-LVCMOS T

RANSLATOR

UFFER

BSOLUTE

AXIMUM

ATINGS

Supply Voltage, V

Inputs, V

Outputs, V

4.6V

-0.5V to V

+ 0.5 V

-0.5V to V

+ 0.5V

NOTE: Stresses beyond those listed under Absolute

Maximum Ratings may cause permanent damage to the

device. These ratings are stress specifications only. Func-

tional operation of product at these conditions or any condi-

tions beyond those listed in the

DC Characteristics

Characteristics

is not implied. Exposure to absolute maxi-

mum rating conditions for extended periods may affect prod-

uct reliability.

Package Thermal Impedance,

112.7°C/W (0 lfpm)

Storage Temperature, T

STG

-65°C to 150°C

ABLE

3A. P

OWER

UPPLY

DC C

HARACTERISTICS

= 3.3V±0.3V, T

= -40°C

85°C

Symbol

Parameter

Positive Supply Voltage

Positive Supply Current

Test Conditions

Minimum

3.0

Typical

3.3

Maximum

3.6

Units

ABLE

3B. LVCMOS / LVTTL DC C

HARACTERISTICS

= 3.3V±0.3V, T

= -40°C

85°C

Symbol

Parameter

Output High Voltage; NOTE 1

Output Low Voltage; NOTE 1

Test Conditions

Minimum

2.6

0.5

Typical

Maximum

Units

NOTE 1: Outputs terminated with 50

to V

/2. See Parameter Measurement Section, 3.3V Output Load Test Circuit.

ABLE

3C. D

IFFERENTIAL

DC C

HARACTERISTICS

= 3.3V±0.3V, T

= -40°C

85°C

Symbol

Parameter

Input High Current

Input Low Current

nCLK0, nCLK1

CLK0, CLK1

nCLK0, nCLK1

CLK0, CLK1

Test Conditions

= V

= 3.6V

= V

= 3.6V

= 0V, V

= 3.6V

= 0V, V

= 3.6V

-150

-5

1.3

- 0.85

Minimum

Typical

Maximum

150

Units

µA

Peak-to-Peak Input Voltage

0.15

Common Mode Input Voltage;

CMR

GND + 0.5

NOTE 1, 2

NOTE 1: For single-ended applications

the maximum input voltage for CLKx, nCLKx is V

+ 0.3V.

NOTE 2: Common mode voltage is defined as V

83023AMI

www.idt.com

REV. B JULY 29, 2010

ICS83023I

UAL

, 1-

-1

IFFERENTIAL

-LVCMOS T

RANSLATOR

UFFER

ABLE

4. AC C

HARACTERISTICS

= 3.3V±0.3V, T

= -40°C

85°C

Symbol Parameter

MAX

Maximum Output Frequency

Propagation Delay; NOTE 1

Output Skew; NOTE 2, 4

Par t-to-Par t Skew; NOTE 3, 4

Buffer Additive Phase Jitter, RMS;

refer to Additive Phase Jitter Section

Output Rise Time

Output Fall Time

Output Duty Cycle

100MHz, Integration Range

(637kHz-10MHz)

0.8V to 2V

≤

166MHz

1.8

Test Conditions

Minimum

Typical

350

2.1

2.4

500

0.14

100

250

400

Maximum

Units

MHz

sk(o)

sk(pp)

jit

odc

f > 166MHz

All parameters measured at f

MAX

unless noted otherwise. See Parameter Measurement Information.

NOTE 1: Measured from the differential input crossing point to V

/2 of the output.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.

Measured at V

/2. Input clocks are phase aligned.

NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages

and with equal load conditions. Using the same type of inputs on each device, the outputs are measured

at V

/2.

NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.

83023AMI

www.idt.com

REV. B JULY 29, 2010

ICS83023I

UAL

, 1-

-1

IFFERENTIAL

-LVCMOS T

RANSLATOR

UFFER

DDITIVE

HASE

ITTER

The spectral purity in a band at a specific offset from the

fundamental compared to the power of the fundamental is

called the

dBc Phase Noise.

This value is normally expressed

using a Phase noise plot and is most often the specified plot

in many applications. Phase noise is defined as the ratio of

the noise power present in a 1Hz band at a specified offset

from the fundamental frequency to the power value of the

fundamental. This ratio is expressed in decibels (dBm) or a

-10

-20

-30

-40

-50

-60

ratio of the power in the 1Hz band to the power in the funda-

mental. When the required offset is specified, the phase noise

is called a

dBc

value, which simply means dBm at a specified

offset from the fundamental. By investigating jitter in the fre-

quency domain, we get a better understanding of its effects

on the desired application over the entire time record of the

signal. It is mathematically possible to calculate an expected

bit error rate given a phase noise plot.

Additive Phase Jitter

@ 100MHz

(12kHz to 20MHz)

= 0.14ps typical

SSB P

HASE

OISE

dBc/H

-70

-80

-90

-100

-110

-120

-130

-140

-150

-160

-170

-180

-190

10k

100k

10M

100M

FFSET

ROM

ARRIER

REQUENCY

)

As with most timing specifications, phase noise measure-

ments have issues. The primary issue relates to the limita-

tions of the equipment. Often the noise floor of the equipment

is higher than the noise floor of the device. This is illustrated

above. The device meets the noise floor of what is shown, but

can actually be lower. The phase noise is dependant on the

input source and measurement equipment.

83023AMI

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REV. B JULY 29, 2010

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83023AMIT Related Products

	83023AMIT	83023AMI
Description	Low Skew Clock Driver, 83023 Series, 1 True Output(s), 0 Inverted Output(s), PDSO8, 3.80 X 4.80 MM, 1.47 MM HEIGHT, MS-012, SOIC-8	Low Skew Clock Driver, 83023 Series, 1 True Output(s), 0 Inverted Output(s), PDSO8, 3.80 X 4.80 MM, 1.47 MM HEIGHT, MS-012, SOIC-8
Is it lead-free?	Contains lead	Contains lead
Is it Rohs certified?	incompatible	incompatible
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	SOIC	SOIC
package instruction	3.80 X 4.80 MM, 1.47 MM HEIGHT, MS-012, SOIC-8	3.80 X 4.80 MM, 1.47 MM HEIGHT, MS-012, SOIC-8
Contacts	8	8
Reach Compliance Code	not_compliant	not_compliant
ECCN code	EAR99	EAR99
series	83023	83023
Input adjustment	DIFFERENTIAL	DIFFERENTIAL
JESD-30 code	R-PDSO-G8	R-PDSO-G8
JESD-609 code	e0	e0
length	4.9 mm	4.9 mm
Logic integrated circuit type	LOW SKEW CLOCK DRIVER	LOW SKEW CLOCK DRIVER
Humidity sensitivity level	1	1
Number of functions	2	2
Number of terminals	8	8
Actual output times	1	1
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SOP	SOP
Encapsulate equivalent code	SOP8,.25	SOP8,.25
Package shape	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	240	240
power supply	3.3 V	3.3 V
Prop。Delay @ Nom-Sup	2.4 ns	2.4 ns
propagation delay (tpd)	2.4 ns	2.4 ns
Certification status	Not Qualified	Not Qualified
Same Edge Skew-Max（tskwd）	0.06 ns	0.06 ns
Maximum seat height	1.75 mm	1.75 mm
Maximum supply voltage (Vsup)	3.6 V	3.6 V
Minimum supply voltage (Vsup)	3 V	3 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V
surface mount	YES	YES
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal surface	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING	GULL WING
Terminal pitch	1.27 mm	1.27 mm
Terminal location	DUAL	DUAL
Maximum time at peak reflow temperature	30	30
width	3.9 mm	3.9 mm

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