LOW SKEW, 1-TO-4 LVCMOS/LVTTL
FANOUT BUFFER
ICS8304
G
ENERAL
D
ESCRIPTION
The ICS8304 is a low skew, 1-to-4 Fanout Buffer. The
ICS8304 is characterized at full 3.3V for input (V
DD
), and
mixed 3.3V and 2.5V for output operating supply modes
(V
DDO
). Guaranteed output and par t-to-par t skew character-
istics make the ICS8304 ideal for those clock distribution
applications demanding well defined performance and re-
peatability.
F
EATURES
•
Four LVCMOS / LVTTL outputs
•
LVCMOS / LVTTL clock input
•
CLK can accept the following input levels: LVCMOS, LVTTL
•
Maximum output frequency: 200MHz
•
Additive phase jitter, RMS: 0.173ps (typical) @ 3.3V
•
Output skew: 45ps (maximum) @ 3.3V
•
Part-to-part skew: 500ps (maximum)
•
Small 8 lead SOIC package saves board space
•
3.3V input, outputs may be either 3.3V or 2.5V supply modes
•
0°C to 70°C ambient operating temperature
•
Available in both standard (RoHS 5) and lead-free (RoHS 6)
compliant packages
B
LOCK
D
IAGRAM
Q0
Q1
CLK
Pulldown
Q2
P
IN
A
SSIGNMENT
V
DDO
V
DD
CLK
GND
1
2
3
4
8
7
6
5
Q3
Q2
Q1
Q0
ICS8304
8-Lead SOIC
3.9mm x 4.9mm, x 1.375mm package body
M Package
Top View
Q3
IDT
™
/ ICS
™
LVCMOS/LVTTL FANOUT BUFFER
1
ICS8304AM REV. H OCTOBER 29, 2010
ICS8304
LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
Number
1
2
3
4
5
6
7
8
Name
Name
V
DDO
V
DD
CLK
GND
Q0
Q1
Q2
Q3
Power
Power
Input
Power
Type
Type
Description
Description
Output supply pin.
Positive supply pin.
Pulldown LVCMOS / LVTTL clock input.
Power supply ground.
Single clock output. LVCMOS / LVTTL interface levels.
Single clock output. LVCMOS / LVTTL interface levels.
Single clock output. LVCMOS / LVTTL interface levels.
Single clock output. LVCMOS / LVTTL interface levels.
Output
Output
Output
Output
NOTE:
Pulldown
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
C
PD
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
(per output)
Input Pulldown Resistor
Output Impedance
Test Conditions
Minimum
Typical
4
V
DD
, V
DDO
= 3.465V
51
5
7
12
15
Maximum
Units
pF
pF
kΩ
Ω
IDT
™
/ ICS
™
LVCMOS/LVTTL FANOUT BUFFER
2
ICS8304AM REV. H OCTOBER 29, 2010
ICS8304
LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Package Thermal Impedance,
θ
JA
112.7°C/W (0 lfpm)
Storage Temperature, T
STG
-65°C to 150°C
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Power Supply Voltage
Output Power Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
Typical
3.3
3.3
Maximum
3.465
3.465
15
8
Units
V
V
mA
mA
T
ABLE
3B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDO
I
DD
I
DDO
Parameter
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
2.375
Typical
3.3
2.5
Maximum
3.465
2.625
15
8
Units
V
V
mA
mA
T
ABLE
3C. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
IH
V
IL
I
IH
I
IL
V
OH
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Output High Voltage
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
Refer to NOTE 1
I
OH
= -16mA
I
OH
= -100uA
Refer to NOTE 1
V
OL
Output Low Voltage
I
OL
= 16mA
I
OL
= 100uA
-5
2.6
2.9
3
0.5
0.25
0.15
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
1.3
150
Units
V
V
µA
µA
V
V
V
V
V
V
NOTE 1: Outputs terminated with 50
Ω
to V
DDO
/2. See Parameter Measurement Section, "3.3V Output Load Test Circuit".
IDT
™
/ ICS
™
LVCMOS/LVTTL FANOUT BUFFER
3
ICS8304AM REV. H OCTOBER 29, 2010
ICS8304
LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER
T
ABLE
3D. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
V
IH
V
IL
I
IH
I
IL
V
OH
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Output High Voltage; NOTE 1
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
-5
2.1
0.5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
1.3
150
Units
V
V
µA
µA
V
V
Output Low Voltage; NOTE 1
V
OL
NOTE 1: Outputs terminated with 50
Ω
to V
DDO
/2. See Parameter Measurement Section,
"3.3V/2.5V Output Load Test Circuit".
T
ABLE
4A. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol Parameter
f
MAX
tp
LH
Maximum Output Frequency
Propagation Delay, Low-to-High;
NOTE 1
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
Output Skew; NOTE 2, 4
Par t-to-Par t Skew; NOTE 3, 4
Output Rise Time
Output Fall Time
30% to 70%
30% to 70%
250
250
IJ 166MHz
166MHz < f
≤
189.5MHz
125MHz, Integration Range:
12kHz – 20MHz
ƒ = 133MHz
2.0
2. 0
0.173
45
500
500
500
60
Test Conditions
Minimum
Typical
Maximum
200
3. 3
3.4
Units
MHz
ns
ns
ps
ps
ps
ps
ps
%
t
jit
t
sk(o)
t
sk(pp)
t
R
t
F
odc
Output Duty Cycle
f
≤
189.5MHz
40
All parameters measured at f
MAX
unless noted otherwise.
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDO
/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at V
DDO
/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
T
ABLE
4B. AC C
HARACTERISTICS
,
V
DD
= 3.3V±5%, V
DDO
= 2.5V±5%, T
A
= 0°C
TO
70°C
Symbol Parameter
f
MAX
tp
LH
Maximum Output Frequency
Propagation Delay, Low-to-High; NOTE 1
Output Skew; NOTE 2, 4
Par t-to-Par t Skew; NOTE 3, 4
Output Rise Time
Output Fall Time
30% to 70%
30% to 70%
f
≤
189.5MHz
250
250
40
IJ 166MHz
166MHz < f
≤
189.5MHz
ƒ = 133MHz
2.3
2.15
Test Conditions
Minimum
Typical
Maximum
189.5
3.7
3.55
60
500
500
500
60
Units
MHz
ns
ns
ps
ps
ps
ps
%
t
sk(o)
t
sk(pp)
t
R
t
F
odc
Output Duty Cycle
For NOTES, please see above Table 4A.
IDT
™
/ ICS
™
LVCMOS/LVTTL FANOUT BUFFER
4
ICS8304AM REV. H OCTOBER 29, 2010
ICS8304
LOW SKEW, 1-TO-4 LVCMOS/LVTTL FANOUT BUFFER
A
DDITIVE
P
HASE
J
ITTER
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the
dBc Phase Noise.
This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz
band to the power in the fundamental. When the required offset
is specified, the phase noise is called a
dBc
value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
Additive Phase Jitter
@ 125MHz
(12kHz to 20MHz) = 0.173ps typical
SSB P
HASE
N
OISE
dBc/H
Z
O
FFSET
F
ROM
C
ARRIER
F
REQUENCY
(H
Z
)
As with most timing specifications, phase noise measurements
has issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The device
meets the noise floor of what is shown, but can actually be lower.
The phase noise is dependant on the input source and
measurement equipment.
IDT
™
/ ICS
™
LVCMOS/LVTTL FANOUT BUFFER
5
ICS8304AM REV. H OCTOBER 29, 2010
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