4:2 Differential Clock/Data
Multiplexer
Datasheet
831742I
Description
The 831742I is a high-performance, differential HCSL clock/data
multiplexer and fanout buffer. The device is designed for the
multiplexing and fanout of high-frequency clock and data signals.
The device has four differential, selectable clock/data inputs. The
selected input signal is distributed to two low-skew differential HCSL
outputs. Each input pair accepts HCSL, LVDS and LVPECL levels.
The 831742I is characterized to operate from a 3.3V power supply.
Guaranteed input, output-to-output and part-to-part skew
characteristics make the 831742I ideal for those clock and data
distribution applications demanding well-defined performance and
repeatability. The 831742I supports the clock multiplexing and
distribution of PCI Express (2.5Gb/s), Gen 2 (5Gb/s) and
Gen 3 (8Gb/s) clock signals.
Features
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4:2 differential clock/data multiplexer with fanout
Four selectable, differential input pairs
Each differential input pair can accept the following levels: HCSL,
LVDS and LVPECL
Two differential HCSL output pairs
Maximum input/output clock frequency: 700MHz
Maximum input/output data rate: 1400Mb/s (NRZ)
LVCMOS interface levels for all control inputs
PCI Express (2.5Gb/s), Gen 2 (5 Gb/s) and Gen 3 (8 Gb/s) clock
jitter compliant
Input skew: 110ps max
Part-to-part skew: 225ps max
Full 3.3V supply voltage
Available in lead-free (RoHS 6)
-40°C to 85°C ambient operating temperature
Block Diagram
IREF
CLK0
nCLK0
CLK1
nCLK1
CLK
nCLK
CLK3
nCLK3
Pin Assignment
Pulldown
Pullup/down
Pulldown
Pullup/down
Pulldown
Pullup/down
Pulldown
Pullup/down
Pulldown
Pulldown
0 0
0 1
1 0
1 1
QA
nQA
Q
nQ
GND
CLK0
nCLK0
V
DD
CLK1
nCLK1
CLK2
nCLK2
GND
CLK3
nCLK3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
SEL1
IREF
SEL0
V
DD
nQB
QB
nQA
QA
V
DD
GND
nOEB
nOEA
831742AGI
24-Lead TSSOP
4.4mm x 7.8mm x 0.925mm package body
G Package
Top View
nOEA
Pullup
Pullup
©2017 Integrated Device Technology, Inc
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831742I Datasheet
Table 1. Pin Descriptions
Number
1, 9, 15
2
3
4, 12,
16, 21
5
6
7
8
10
11
13
14
17, 18
19, 20
22, 24
23
Name
GND
CLK0
nCLK0
V
DD
CLK1
nCLK1
CLK2
nCLK2
CLK3
nCLK3
nOEA
nOEB
QA, nQA
QB, nQB
SEL0, SEL1
IREF
Power
Input
Input
Power
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Input
Input
Pulldown
Pulldown
Pulldown/Pullup
Pulldown
Pulldown/Pullup
Pulldown
Pulldown/Pullup
Pullup
Pullup
Pulldown
Pulldown/Pullup
Type
Description
Power supply ground.
Non-inverting clock/data input.
Inverting differential clock/data input. V
DD
/2 default when left floating.
Positive power supply.
Non-inverting clock/data input.
Inverting differential clock/data input. V
DD
/2 default when left floating.
Non-inverting clock/data input.
Inverting differential clock/data input. V
DD
/2 default when left floating.
Non-inverting clock/data input.
Inverting differential clock/data input. V
DD
/2 default when left floating.
Output enable for the QA output. See Table 3A for function.
LVCMOS/LVTTL interface levels.
Output enable for the QB output. See Table 3B for function.
LVCMOS/LVTTL interface levels.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Differential clock/data Input select. See Table 3C for function.
LVCMOS/LVTTL interface levels.
An external fixed precision resistor (475
) from this pin to ground provides a
reference current used for the differential current-mode QX, nQX outputs.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
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831742I Datasheet
Function Tables
Table 3A. nOEA Configuration Table
Input
nOEA
0
1 (default)
Operation
Output QA, nQA is enabled.
Output QA, nQA is in a high-impedance state.
Table 3B. nOEB Configuration Table
Input
nOEB
0
1 (default)
Operation
Output QB, nQB is enabled.
Output QB, nQB is in a high-impedance state.
NOTE: nOEA is an asynchronous control.
NOTE: nOEB is an asynchronous control.
Table 3C. SELx Configuration Table
Input
SEL1
0 (default)
0
1
1
SEL0
0 (default)
1
0
1
Selected
CLK0, nCLK0
CLK1, nCLK1
CLK2, nCLK2
CLK3, nCLK3
NOTE: SEL1 and SEL0 are asynchronous controls
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831742I Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC
Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DD
+ 0.5V
87.8°C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= 3.3V ± 0.3V, T
A
= -40°C to 85°C
Symbol
V
DD
I
DD
Parameter
Positive Supply Voltage
Power Supply Current
Outputs Unloaded
Test Conditions
Minimum
3.0
Typical
3.3
Maximum
3.6
26
Units
V
mA
Table 4B. LVCMOS/LVTTL Input DC Characteristics,
V
DD
= 3.3V ± 0.3V, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
nOEA, nOEB
Input High Current
SEL0, SEL1
nOEA, nOEB
I
IL
Input Low Current
SEL0, SEL1
V
DD
= V
IN
= 3.6V
V
DD
= V
IN
= 3.6V
V
DD
= 3.6V, V
IN
= 0V
V
DD
= 3.6V, V
IN
= 0V
-150
-5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
5
150
Units
V
V
µA
µA
µA
µA
Table 4C. Differential DC Characteristics,
V
DD
= 3.3V ± 0.3V, T
A
= -40°C to 85°C
Symbol
I
IH
I
IL
V
PP
V
CMR
Parameter
Input
High Current
Input
Low Current
CLK0, nCLK0; CLK1, nCLK1;
CLK2, nCLK2; CLK3, nCLK3
CLK[0:3]
nCLK[0:3]
Test Conditions
V
DD
= V
IN
= 3.6V
V
DD
= 3.6V, V
IN
= 0V
V
DD
= 3.6V, V
IN
= 0V
-5
-150
0.15
0.5
1.3
V
DD
– 0.85
Minimum
Typical
Maximum
150
Units
µA
µA
µA
V
V
Peak-to-Peak Voltage; NOTE 1
Common Mode Input Voltage; NOTE 1, 2
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as V
IH
.
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831742I Datasheet
AC Electrical Characteristics
Table 5A. PCI Express Jitter Specifications,
V
DD
= 3.3V ± 0.3V, T
A
= -40°C to 85°C
Symbol
t
j
(PCIe Gen 1)
t
REFCLK_HF_RMS
(PCIe Gen 2)
t
REFCLK_LF_RMS
(PCIe Gen 2)
t
REFCLK_RMS
(PCIe Gen 3)
Parameter
Phase Jitter
Peak-to-Peak;
NOTE 1, 4
Phase Jitter RMS;
NOTE 2, 4
Phase Jitter RMS;
NOTE 2, 4
Phase Jitter RMS;
NOTE 3, 4
Test Conditions
ƒ = 100MHz, 100MHz Input
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
ƒ = 100MHz, 100MHz Input
High Band: 1.5MHz - Nyquist
(clock frequency/2)
ƒ = 100MHz, 100MHz Input
Low Band: 10kHz - 1.5MHz
ƒ = 100MHz, 100MHz Input
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
Minimum
Typical
10
Maximum
21
PCIe Industry
Specification
86
Units
ps
1
2.5
3.1
ps
0.05
0.2
3.0
ps
0.2
0.8
0.8
ps
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions. Measurements performed with a PCI Express compliant input source. For additional information,
refer to the
PCI Express Application Note section
in the datasheet.
NOTE 1: Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1
is 86ps peak-to-peak for a sample size of 10
6
clock periods.
NOTE 2: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and
reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for t
REFCLK_HF_RMS
(High
Band) and 3.0ps RMS for t
REFCLK_LF_RMS
(Low Band).
NOTE 3: RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the
PCI Express
Base Specification Revision 0.7, October 2009
and is subject to change pending the final release version of the specification.
NOTE 4: This parameter is guaranteed by characterization. Not tested in production.
©2017 Integrated Device Technology, Inc
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