831742AGILFT datasheet, PDF - EEWORLD Datasheet

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831742AGILFT: DescriptionTSSOP-24, Reel; Categorylogic logic; File Size689KB，19 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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831742AGILFT Overview

TSSOP-24, Reel

831742AGILFT Parametric

Parameter Name	Attribute value
Brand Name	Integrated Device Technology
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	TSSOP
package instruction	TSSOP-24
Contacts	24
Manufacturer packaging code	PGG24
Reach Compliance Code	compliant
ECCN code	EAR99
series	831742
Input adjustment	DIFFERENTIAL MUX
JESD-30 code	R-PDSO-G24
JESD-609 code	e3
length	7.8 mm
Logic integrated circuit type	LOW SKEW CLOCK DRIVER
Humidity sensitivity level	1
Number of functions	1
Number of inverted outputs
Number of terminals	24
Actual output times	4
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP24,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Prop。Delay @ Nom-Sup	2.5 ns
propagation delay (tpd)	2.5 ns
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.015 ns
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	4.4 mm
minfmax	700 MHz

831742AGILFT Preview

4:2 Differential Clock/Data

Multiplexer

Datasheet

831742I

Description

The 831742I is a high-performance, differential HCSL clock/data

multiplexer and fanout buffer. The device is designed for the

multiplexing and fanout of high-frequency clock and data signals.

The device has four differential, selectable clock/data inputs. The

selected input signal is distributed to two low-skew differential HCSL

outputs. Each input pair accepts HCSL, LVDS and LVPECL levels.

The 831742I is characterized to operate from a 3.3V power supply.

Guaranteed input, output-to-output and part-to-part skew

characteristics make the 831742I ideal for those clock and data

distribution applications demanding well-defined performance and

repeatability. The 831742I supports the clock multiplexing and

distribution of PCI Express (2.5Gb/s), Gen 2 (5Gb/s) and

Gen 3 (8Gb/s) clock signals.

Features

•

4:2 differential clock/data multiplexer with fanout

Four selectable, differential input pairs

Each differential input pair can accept the following levels: HCSL,

LVDS and LVPECL

Two differential HCSL output pairs

Maximum input/output clock frequency: 700MHz

Maximum input/output data rate: 1400Mb/s (NRZ)

LVCMOS interface levels for all control inputs

PCI Express (2.5Gb/s), Gen 2 (5 Gb/s) and Gen 3 (8 Gb/s) clock

jitter compliant

Input skew: 110ps max

Part-to-part skew: 225ps max

Full 3.3V supply voltage

Available in lead-free (RoHS 6)

-40°C to 85°C ambient operating temperature

Block Diagram

IREF

CLK0

nCLK0

CLK1

nCLK1

CLK

nCLK

CLK3

nCLK3

Pin Assignment

Pulldown

Pullup/down

Pulldown

Pullup/down

Pulldown

Pullup/down

Pulldown

Pullup/down

Pulldown

0 0

0 1

1 0

1 1

nQA

GND

CLK0

nCLK0

CLK1

nCLK1

CLK2

nCLK2

GND

CLK3

nCLK3

SEL1

IREF

SEL0

nQB

nQA

GND

nOEB

nOEA

831742AGI

24-Lead TSSOP

4.4mm x 7.8mm x 0.925mm package body

G Package

Top View

nOEA

Pullup

August 17, 2017

831742I Datasheet

Table 1. Pin Descriptions

Number

1, 9, 15

4, 12,

16, 21

17, 18

19, 20

22, 24

Name

GND

CLK0

nCLK0

CLK1

nCLK1

CLK2

nCLK2

CLK3

nCLK3

nOEA

nOEB

QA, nQA

QB, nQB

SEL0, SEL1

IREF

Power

Input

Power

Input

Output

Input

Pulldown

Pulldown/Pullup

Pulldown

Pulldown/Pullup

Pulldown

Pulldown/Pullup

Pullup

Pulldown

Pulldown/Pullup

Type

Description

Power supply ground.

Non-inverting clock/data input.

Inverting differential clock/data input. V

/2 default when left floating.

Positive power supply.

Non-inverting clock/data input.

Inverting differential clock/data input. V

/2 default when left floating.

Non-inverting clock/data input.

Inverting differential clock/data input. V

/2 default when left floating.

Non-inverting clock/data input.

Inverting differential clock/data input. V

/2 default when left floating.

Output enable for the QA output. See Table 3A for function.

LVCMOS/LVTTL interface levels.

Output enable for the QB output. See Table 3B for function.

LVCMOS/LVTTL interface levels.

Differential output pair. HCSL interface levels.

Differential clock/data Input select. See Table 3C for function.

LVCMOS/LVTTL interface levels.

An external fixed precision resistor (475



) from this pin to ground provides a

reference current used for the differential current-mode QX, nQX outputs.

NOTE:

Pullup

and

Pulldown

refer to internal input resistors. See Table 2,

Pin Characteristics,

for typical values.

Table 2. Pin Characteristics

Symbol

PULLUP

PULLDOWN

Parameter

Input Capacitance

Input Pullup Resistor

Input Pulldown Resistor

Test Conditions

Minimum

Typical

Maximum

Units



August 17, 2017

831742I Datasheet

Function Tables

Table 3A. nOEA Configuration Table

Input

nOEA

1 (default)

Operation

Output QA, nQA is enabled.

Output QA, nQA is in a high-impedance state.

Table 3B. nOEB Configuration Table

Input

nOEB

1 (default)

Operation

Output QB, nQB is enabled.

Output QB, nQB is in a high-impedance state.

NOTE: nOEA is an asynchronous control.

NOTE: nOEB is an asynchronous control.

Table 3C. SELx Configuration Table

Input

SEL1

0 (default)

SEL0

0 (default)

Selected

CLK0, nCLK0

CLK1, nCLK1

CLK2, nCLK2

CLK3, nCLK3

NOTE: SEL1 and SEL0 are asynchronous controls

August 17, 2017

831742I Datasheet

Absolute Maximum Ratings

NOTE: Stresses beyond those listed under

Absolute Maximum Ratings

may cause permanent damage to the device. These ratings are stress

specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the

DC Characteristics or AC

Characteristics

is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

Item

Supply Voltage, V

Inputs, V

Outputs, V

Package Thermal Impedance,



Storage Temperature, T

STG

Rating

4.6V

-0.5V to V

+ 0.5V

-0.5V to V

+ 0.5V

87.8°C/W (0 mps)

-65C to 150C

DC Electrical Characteristics

Table 4A. Power Supply DC Characteristics,

= 3.3V ± 0.3V, T

= -40°C to 85°C

Symbol

Parameter

Positive Supply Voltage

Power Supply Current

Outputs Unloaded

Test Conditions

Minimum

3.0

Typical

3.3

Maximum

3.6

Units

Table 4B. LVCMOS/LVTTL Input DC Characteristics,

= 3.3V ± 0.3V, T

= -40°C to 85°C

Symbol

Parameter

Input High Voltage

Input Low Voltage

nOEA, nOEB

Input High Current

SEL0, SEL1

nOEA, nOEB

Input Low Current

SEL0, SEL1

= V

= 3.6V

= V

= 3.6V

= 3.6V, V

= 0V

= 3.6V, V

= 0V

-150

-5

Test Conditions

Minimum

-0.3

Typical

Maximum

+ 0.3

0.8

150

Units

µA

Table 4C. Differential DC Characteristics,

= 3.3V ± 0.3V, T

= -40°C to 85°C

Symbol

CMR

Parameter

Input

High Current

Input

Low Current

CLK0, nCLK0; CLK1, nCLK1;

CLK2, nCLK2; CLK3, nCLK3

CLK[0:3]

nCLK[0:3]

Test Conditions

= V

= 3.6V

= 3.6V, V

= 0V

= 3.6V, V

= 0V

-5

-150

0.15

0.5

1.3

– 0.85

Minimum

Typical

Maximum

150

Units

µA

Peak-to-Peak Voltage; NOTE 1

Common Mode Input Voltage; NOTE 1, 2

NOTE 1: V

should not be less than -0.3V.

NOTE 2: Common mode input voltage is defined as V

August 17, 2017

831742I Datasheet

AC Electrical Characteristics

Table 5A. PCI Express Jitter Specifications,

= 3.3V ± 0.3V, T

= -40°C to 85°C

Symbol

(PCIe Gen 1)

REFCLK_HF_RMS

(PCIe Gen 2)

REFCLK_LF_RMS

(PCIe Gen 2)

REFCLK_RMS

(PCIe Gen 3)

Parameter

Phase Jitter

Peak-to-Peak;

NOTE 1, 4

Phase Jitter RMS;

NOTE 2, 4

Phase Jitter RMS;

NOTE 2, 4

Phase Jitter RMS;

NOTE 3, 4

Test Conditions

ƒ = 100MHz, 100MHz Input

Evaluation Band: 0Hz - Nyquist

(clock frequency/2)

ƒ = 100MHz, 100MHz Input

High Band: 1.5MHz - Nyquist

(clock frequency/2)

ƒ = 100MHz, 100MHz Input

Low Band: 10kHz - 1.5MHz

ƒ = 100MHz, 100MHz Input

Evaluation Band: 0Hz - Nyquist

(clock frequency/2)

Minimum

Typical

Maximum

PCIe Industry

Specification

Units

2.5

3.1

0.05

0.2

3.0

0.2

0.8

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium

has been reached under these conditions. Measurements performed with a PCI Express compliant input source. For additional information,

refer to the

PCI Express Application Note section

in the datasheet.

NOTE 1: Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1

is 86ps peak-to-peak for a sample size of 10

clock periods.

NOTE 2: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and

reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for t

REFCLK_HF_RMS

(High

Band) and 3.0ps RMS for t

REFCLK_LF_RMS

(Low Band).

NOTE 3: RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the

PCI Express

Base Specification Revision 0.7, October 2009

and is subject to change pending the final release version of the specification.

NOTE 4: This parameter is guaranteed by characterization. Not tested in production.

August 17, 2017

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831742AGILFT Related Products

	831742AGILFT	831742AGILF
Description	TSSOP-24, Reel	TSSOP-24, Tube
Brand Name	Integrated Device Technology	Integrated Device Technology
Is it lead-free?	Lead free	Lead free
Is it Rohs certified?	conform to	conform to
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	TSSOP	TSSOP
package instruction	TSSOP-24	TSSOP, TSSOP24,.25
Contacts	24	24
Manufacturer packaging code	PGG24	PGG24
Reach Compliance Code	compliant	compliant
ECCN code	EAR99	EAR99
series	831742	831742
Input adjustment	DIFFERENTIAL MUX	DIFFERENTIAL MUX
JESD-30 code	R-PDSO-G24	R-PDSO-G24
JESD-609 code	e3	e3
length	7.8 mm	7.8 mm
Logic integrated circuit type	LOW SKEW CLOCK DRIVER	LOW SKEW CLOCK DRIVER
Humidity sensitivity level	1	1
Number of functions	1	1
Number of terminals	24	24
Actual output times	4	4
Maximum operating temperature	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C
Output characteristics	3-STATE	3-STATE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSSOP	TSSOP
Encapsulate equivalent code	TSSOP24,.25	TSSOP24,.25
Package shape	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	260	260
power supply	3.3 V	3.3 V
Prop。Delay @ Nom-Sup	2.5 ns	2.5 ns
propagation delay (tpd)	2.5 ns	2.5 ns
Certification status	Not Qualified	Not Qualified
Same Edge Skew-Max（tskwd）	0.015 ns	0.015 ns
Maximum seat height	1.2 mm	1.2 mm
Maximum supply voltage (Vsup)	3.6 V	3.6 V
Minimum supply voltage (Vsup)	3 V	3 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V
surface mount	YES	YES
Temperature level	INDUSTRIAL	INDUSTRIAL
Terminal surface	Matte Tin (Sn)	Matte Tin (Sn)
Terminal form	GULL WING	GULL WING
Terminal pitch	0.65 mm	0.65 mm
Terminal location	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED
width	4.4 mm	4.4 mm
minfmax	700 MHz	700 MHz

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