LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-
LVPECL/ECL FANOUT BUFFER
ICS853111A
G
ENERAL
D
ESCRIPTION
The ICS853111A is a low skew, high perfor-
mance 1-to-10 Differential-to-2.5V/3.3V LVPECL/
HiPerClockS™
E C L Fa n o u t B u f fe r a n d a m e m b e r o f t h e
H i Pe r C l o ckS ™ fa m i l y o f H i g h Pe r fo r m a n c e
Clock Solutions from I DT. The ICS853111A
is characterized to operate from either a 2.5V, 3.3V or a
5V power supply. Guaranteed output and par t-to-par t skew
characteristics make the ICS853111A ideal for those clock
distribution applications demanding well defined perfor-
mance and repeatability.
F
EATURES
•
Ten differential LVPECL outputs
•
Two selectable differential LVPECL PCLK/nPCLK clock inputs
•
PCLK, nPCLK pairs can accept the following differential
input levels: LVPECL, LVDS, CML, SSTL
•
Maximum output frequency: >3GHz
•
Translates any single ended input signal to 3.3V LVPECL
levels with resistor bias on nPCLK input
•
Additive phase jitter, RMS: <0.3ps (typical)
•
Output skew: 23ps (typical)
•
Part-to-part skew: 85ps (typical)
•
Propagation delay: 705ps (typical)
•
LVPECL mode operating voltage supply range:
V
CC
= 2.375V to 5.25V, V
EE
= 0V
•
ECL mode operating voltage supply range:
V
CC
= 0V, V
EE
= -5.25V to -2.375V
•
-40°C to 85°C ambient operating temperature
•
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
IC
S
B
LOCK
D
IAGRAM
PCLK0
nPCLK0
PCLK1
nPCLK1
0
1
Q0
nQ0
Q1
nQ1
P
IN
A
SSIGNMENT
nQ3
nQ4
nQ5
nQ6
Q3
Q4
Q5
Q6
24 23 22 21 20 19 18 17
V
CCO
25
26
27
28
29
30
31
32
1
V
CC
16
15
14
V
CCO
Q7
nQ7
Q8
nQ8
Q9
nQ9
V
CCO
Q2
nQ2
CLK_SEL
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Q8
nQ8
Q9
nQ9
nQ2
Q2
nQ1
Q1
nQ0
Q0
V
CCO
ICS853111A
13
12
11
10
9
V
BB
2
CLK_SEL
3
PCLK0
4
nPCLK0
5
VBB
6
PCLK1
7
nPCLK1
8
V
EE
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
IDT
™
/ ICS
™
1-TO-10, LVPECL/ECL FANOUT BUFFER
1
ICS853111AY REV. C OCTOBER 23, 2008
ICS853111A
LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3
4
5
6
7
8
9, 16, 25, 32
10, 11
12, 13
14, 15
17, 18
19, 20
21, 22
23 , 2 4
26, 27
28, 29
30, 31
Name
V
CC
CLK_SEL
PCLK0
nPCLK0
V
BB
PCLK1
nPCLK1
V
EE
V
CCO
nQ9, Q9
nQ8, Q8
nQ7, Q7
nQ6, Q6
nQ5, Q5
nQ4, Q4
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
Power
Input
Input
Input
Output
Input
Input
Power
Power
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Pulldown
Pullup/Pulldown
Pulldown
Pulldown
Pullup/Pulldown
Type
Description
Positive supply pin.
Clock select input. When HIGH, selects PCLK1, nPCLK1 inputs.
When LOW, selects PCLK0, nPCLK0 inputs.
LVCMOS / LVTTL interface levels.
Non-inver ting differential clock input.
Inver ting differential LVPECL clock input.
V
CC
/2 default when left floating.
Bias voltage.
Non-inver ting differential clock input.
Inver ting differential LVPECL clock input.
V
CC
/2 default when left floating.
Negative supply pin.
Output supply pins.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
R
PULLDOWN
R
VCC/
2
Parameter
Input Pulldown Resistor
Pullup/Pulldown Resistors
Test Conditions
Minimum
Typical
75
50
Maximum
Units
kΩ
kΩ
T
ABLE
3A. C
LOCK
I
NPUT
F
UNCTION
T
ABLE
Inputs
PCLKx
0
1
0
1
nPCLKx
1
0
Biased;
NOTE 1
Biased;
NOTE 1
Outputs
Q0:Q9
LOW
HIGH
LOW
HIGH
nQ0:Q9
HIGH
LOW
HIGH
LOW
Input to Output Mode
Differential to Differential
Differential to Differential
Single Ended to Differential
Single Ended to Differential
Polarity
Non Inver ting
Non Inver ting
Non Inver ting
Non Inver ting
T
ABLE
3B. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
Inputs
CLK_SEL
0
1
Selected Source
PCLK0, nPCLK0
PCLK1, nPCLK1
Biased;
0
HIGH
LOW
Single Ended to Differential
Inver ting
NOTE 1
Biased;
1
LOW
HIGH
Single Ended to Differential
Inver ting
NOTE 1
NOTE 1: Please refer to the Application Information, "Wiring the Differential Input to
Accept Single Ended Levels".
IDT
™
/ ICS
™
1-TO-10, LVPECL/ECL FANOUT BUFFER
2
ICS853111AY REV. C OCTOBER 23, 2008
ICS853111A
LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Negative Supply Voltage, V
EE
Inputs, V
I
(LVPECL mode)
Inputs, V
I
(ECL mode)
Outputs, I
O
Continuous Current
V
BB
Sink/Source, I
BB
Operating Temperature Range, T
A
Storage Temperature, T
STG
Package Thermal Impedance,
θ
JA
(Junction-to-Ambient)
6V (LVPECL mode, V
EE
= 0)
-6V (ECL mode, V
CC
= 0)
-0.5V to V
CC
+ 0.5 V
0.5V to V
EE
- 0.5V
50mA
Surge Current
± 0.5mA
-40°C to +85°C
-65°C to 150°C
37.8°C/W (0 lfpm)
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Characteris-
tics
is not implied. Exposure to absolute maximum rating con-
ditions for extended periods may affect product reliability.
100mA
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 2.375V
TO
3.8V; V
EE
= 0V
Symbol
V
CC
I
EE
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
3.3
Maximum
5.25
85
Units
V
mA
T
ABLE
4B. LVPECL DC C
HARACTERISTICS
,
V
CC
= 3.3V; V
EE
= 0V
Symbol
V
OH
V
OL
V
IH
V
IL
V
BB
V
PP
V
CMR
I
IH
I
IL
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Input High Voltage, Single-Ended
Input Low Voltage, Single-Ended
Output Voltage Reference;
NOTE 2
Peak-to-Peak Input Voltage
Input High Voltage Common
Mode Range; NOTE 3, 4
Input
PCLK0, PCLK1
High Current nPCLK0, nPCLK1
PCLK0, PCLK1
Input
Low Current nPCLK0, nPCLK1
Min
2.175
1.405
2.075
1.43
1.86
150
1.2
800
-40°C
Typ
2.275
1.545
Max
2.38
1.68
2.36
1.765
1.98
1200
3.3
200
-10
-10
Min
2.225
1.425
2.075
1.43
1.86
150
1.2
800
25°C
Typ
2.295
1.52
Max
2.37
1.615
2.36
1.765
1.98
1200
3.3
20 0
-10
Min
2.295
1.44
2.075
1.43
1.86
15 0
1. 2
80 0
85°C
Typ
2.33
1.535
Ma x
2.365
1.63
2.36
1.765
1.98
1200
3. 3
200
Units
V
V
V
V
V
mV
V
µA
µA
µA
-200
-200
-200
Input and output parameters var y 1:1 with V
CC
. V
EE
can var y +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50
Ω
to V
CCO
- 2V.
NOTE 2: Single-ended input operation is limited. V
CC
≥
3V in LVPECL mode.
NOTE 3: Common mode voltage is defined as V
IH
.
NOTE 4: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1 is V
CC
+ 0.3V.
IDT
™
/ ICS
™
1-TO-10, LVPECL/ECL FANOUT BUFFER
3
ICS853111AY REV. C OCTOBER 23, 2008
ICS853111A
LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
T
ABLE
4C. LVPECL DC C
HARACTERISTICS
,
V
CC
= 2.5V; V
EE
= 0V
Symbol
V
OH
V
OL
V
IH
V
IL
V
PP
V
CMR
I
IH
I
IL
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Input High Voltage, Single-Ended
Input Low Voltage, Single-Ended
Peak-to-Peak Input Voltage
Input High Voltage Common
Mode Range; NOTE 2, 3
Input
PCLK0, PCLK1
High Current nPCLK0, nPCLK1
Input
Low Current
PCLK0, PCLK1
-40°C
Min
1.375
0.605
1.275
0.63
150
1.2
80 0
Typ
1.475
0.745
Max
1.58
0.88
1.56
0.965
1200
2.5
200
-10
-10
Min
1.425
0.625
1.275
0.63
150
1.2
800
25°C
Typ
1.495
0.72
Max
1.57
0.815
1.56
0.965
1200
2.5
200
-10
Min
1.495
0.64
1.275
0.63
150
1.2
800
85°C
Typ
1.53
0.735
Ma x
1.565
0.83
-0.83
0.965
1200
2.5
200
Units
V
V
V
V
mV
V
µA
µA
µA
nPCLK0, nPCLK1
-200
-200
-200
Input and output parameters var y 1:1 with V
CC
. V
EE
can var y +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50
Ω
to V
CCO
- 2V.
NOTE 2: Common mode voltage is defined as V
IH
.
NOTE 3: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1 is V
CC
+ 0.3V.
T
ABLE
4D. LVPECL DC C
HARACTERISTICS
,
V
CC
= 5V; V
EE
= 0V
Symbol
V
OH
V
OL
V
IH
V
IL
V
BB
V
PP
V
CMR
I
IH
I
IL
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Input High Voltage, Single-Ended
Input Low Voltage, Single-Ended
Output Voltage Reference;
NOTE 2
Peak-to-Peak Input Voltage
Input High Voltage Common
Mode Range; NOTE 3, 4
Input
PCLK0, PCLK1
High Current nPCLK0, nPCLK1
PCLK0, PCLK1
Input
Low Current nPCLK0, nPCLK1
Min
3.875
3.105
3.775
3.13
3.56
150
1.2
800
-40°C
Typ
3.975
3.245
Max
4.08
3.38
4.06
3.465
3.68
1200
5
200
-10
-10
Min
3.925
3.125
3.775
3.13
3.56
150
1. 2
800
25°C
Typ
3.995
3.22
Max
4.07
3.315
4.06
3.465
3.68
1200
5
20 0
-10
Min
3.995
3.14
3.775
3.13
3.56
150
1.2
800
85°C
Typ
4.0 3
3.235
Ma x
4.065
3.33
4.06
3.465
3.68
1200
5
200
Units
V
V
V
V
V
mV
V
µA
µA
µA
-200
-200
-200
Input and output parameters var y 1:1 with V
CC
. V
EE
can var y +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50
Ω
to V
CCO
- 2V.
NOTE 2: Single-ended input operation is limited. V
CC
≥
3V in LVPECL mode.
NOTE 3: Common mode voltage is defined as V
IH
.
NOTE 4: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1 is V
CC
+ 0.3V.
IDT
™
/ ICS
™
1-TO-10, LVPECL/ECL FANOUT BUFFER
4
ICS853111AY REV. C OCTOBER 23, 2008
ICS853111A
LOW SKEW, 1-TO-10, DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER
T
ABLE
4E. ECL DC C
HARACTERISTICS
,
V
CC
= 0V; V
EE
= -5.25V
TO
-2.375V
Symbol
V
OH
V
OL
V
IH
V
IL
V
BB
V
PP
V
CMR
I
IH
I
IL
Parameter
Output High Voltage;
NOTE 1
Output Low Voltage;
NOTE 1
Input High Voltage,
Single-Ended
Input Low Voltage,
Single-Ended
Output Voltage Reference;
NOTE 2
Peak-to-Peak
Input Voltage
Input High Voltage
Common Mode Range;
NOTE 3, 4
Input
PCLK[0:1],
High Current nPCLK[0:1]
Input
Low Current
PCLK[0:1]
-40°C
Min
-1.125
-1.895
-1.225
-1.87
-1.44
150
V
EE
+1.2V
800
Typ
-1.025
-1.755
Max
-0.92
-1.62
-0.94
-1.535
-1.32
1200
0
200
-10
-10
Min
-1.075
-1.875
-1.225
-1.87
-1.44
150
V
EE
+1.2V
800
25°C
Typ
-1.005
-1.78
Max
-0.93
-1.685
-0.94
-1.535
-1.32
1200
0
200
-10
Min
-1.005
-1.86
-1.225
-1.87
-1.44
150
V
EE
+1.2V
800
85°C
Typ
-0.97
-1.765
Max
-0.935
-1.67
-0.94
-1.535
-1.32
1200
0
20 0
Units
V
V
V
V
V
mV
V
µA
µA
µA
nPCLK[0:1]
-200
-200
-200
Input and output parameters var y 1:1 with V
CC
. V
EE
can var y +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50
Ω
to V
CCO
- 2V.
NOTE 2: Single-ended input operation is limited. V
CC
≥
3V in LVPECL mode.
NOTE 3: Common mode voltage is defined as V
IH
.
NOTE 4: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1 is V
CC
+ 0.3V.
T
ABLE
5. AC C
HARACTERISTICS
,
V
CC
= 0V; V
EE
= -5.25V
TO
-2.375V
OR
V
CC
= 2.375V
TO
5.25V; V
EE
= 0V
Symbol
f
MAX
t
PD
t
sk(o)
t
sk(pp)
t
ji t
t
R
/t
F
Parameter
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Par t-to-Par t Skew; NOTE 3, 4
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section
Output Rise/Fall Time
20% to 80%
85
570
-40°C
Min
Typ
>3
670
23
85
0.03
200
315
100
770
35
150
605
Max
Mi n
25°C
Typ
>3
70 5
23
85
0.03
200
285
85
805
35
150
665
Max
Min
85°C
Typ
>3
76 5
23
85
0.03
20 0
31 5
87 5
35
150
Max
Units
GHz
ps
ps
ps
ps
ps
All parameters are measured
≤
1GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
IDT
™
/ ICS
™
1-TO-10, LVPECL/ECL FANOUT BUFFER
5
ICS853111AY REV. C OCTOBER 23, 2008
京公网安备 11010802033920号
EEWORLD
