89TTM553BL datasheet, PDF - EEWORLD Datasheet

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89TTM553BL: DescriptionMicroprocessor Circuit, PBGA960, 35 X 35 MM, 1 MM PITCH, FPBGA-960; CategoryThe embedded processor and controller Microcontrollers and processors; File Size150KB，29 Pages; ManufacturerIDT (Integrated Device Technology)

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89TTM553BL Overview

Microprocessor Circuit, PBGA960, 35 X 35 MM, 1 MM PITCH, FPBGA-960

89TTM553BL Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	BGA
package instruction	35 X 35 MM, 1 MM PITCH, FPBGA-960
Contacts	960
Reach Compliance Code	not_compliant
ECCN code	5A991
JESD-30 code	S-PBGA-B960
JESD-609 code	e0
length	35 mm
Number of terminals	960
Maximum operating temperature	85 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	225
Certification status	Not Qualified
Maximum seat height	3.29 mm
Maximum supply voltage	1.89 V
Minimum supply voltage	1.71 V
Nominal supply voltage	1.8 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal surface	TIN LEAD
Terminal form	BALL
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	35 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR CIRCUIT

89TTM553BL Preview

Traffic Manager Co-processor

Data Sheet

89TTM553

Preliminary Information*

Description

The 89TTM553 is a flow-based traffic management co-processor

that can be used in conjunction with the 89TTM552.

It has two major functional parts: the queue manager (QM) and the

FLQ scheduler. The QM is responsible for all the non-bandwidth func-

tions, which include managing up to 1 Million queuing structures,

handling cell and packet arrivals and departures from these queues, and

maintaining a database of congestion management and statistics

parameters for each flow queue (FLQ). The FLQ scheduler is respon-

sible for managing the FLQ bandwidth functions.

The 89TTM553 FLQ scheduler supports traffic scheduling on up to

1M discrete flows. In addition to the scheduling levels provided by the

89TTM552, the 89TTM553 provides one or two levels of additional

scheduling hierarchy. It also provides guaranteed minimum rate,

maximum rate capping, excess rate distribution using weighted fair

queuing (WFQ), byte rate shaping, and dynamic configuration adjust-

ments.

The 89TTM553 stores all the flow-based parameters (and state infor-

mation) that are made available to the 89TTM552 for flow-based

processing. When the 89TTM553 is used with the 89TTM552, conges-

tion and bandwidth management features are enabled at the flow level

as well as at the aggregate-flow level.

89TTM55x Features

Deterministic performance at 10 Gbps wire-speed (35 Mcps)

regardless of the number of flows, traffic size, and patterns.

◆

Up to 256 megabytes of external memory buffer space

(equivalent to a 210 ms buffer at 10 Gbps).

◆

Support (Rx and Tx) for industry-standard SPI-4 phase 2,

NPF Streaming Interface, and CSIX over LVDS.

◆

Hierarchical queuing and precise scheduling:

– Traffic management flexibility.

– Support for up to 4K aggregate flow queues (AFQs), 1K port

queues (PQs), 2K arrival reassembly queues (ARQs), and 1K

output queues/channels (OQs) with no external memory

required. Configurable AFQ-to-port assignments.

– Support for up to 1M discrete flows (FLQs), with queuing for

each flow, using external memory. Configurable mapping of

FLQs into aggregate flow queues.

– Two-level FLQ scheduling mode that supports up to 128K or

256K virtual pipe or subscriber queues with up to 8 or 4 CoS

priority queues each.

– Accurate byte-rate shaping at the FLQ, AFQ and port levels.

◆

Multiple levels of buffer congestion management.

– Hierarchical queue structure and thresholding.

– Congestion indication.

◆

– Dynamic adjustment of thresholds during periods of congestion.

– Packet discard (PD).

– Weighted random early discard (WRED).

– Local congestion indication (CI).

◆

Configurable forwarding based on classification index.

◆

Two ports for obtaining event-based statistics.

◆

Configurable on-chip diagnostic statistics.

◆

Bandwidth management rate guarantee and shaping

mechanisms for each flow, each aggregate flow and each

port queue.

– Priority and weighted bandwidth distribution mechanisms

across groups of flows and aggregate flows.

– Schedules rates as low as 2 kbps for each flow.

– One- and two-level byte-rate FLQ scheduling: maximum and

minimum rates, and strict priority and weighted fair queuing

(WFQ) for each FLQ. Per-flow byte-rate shaping.

– AFQ scheduling with byte-rate shaping: minimum and

maximum rates with VBR MBS and PCR enforcement. Excess

distribution using weighted fair queuing (WFQ) and PRR.

– Port queues: maximum rates with byte-rate scheduling.

◆

Wire-speed logical multicasting.

– Four classes of service.

– Programmable service rate (minimum and excess bandwidth

distribution).

– Programmable thresholds.

– Branch connections can be added and deleted during live

traffic.

– Traffic management features on all multicast roots and

branches.

◆

Multicast label generation for spatial multicast support.

◆

Integrated wire-speed AAL-5 segmentation and reassembly

(AAL-5 CPCS SAR) in the datapath.

◆

32-bit processor interface running at up to 66 MHz with

integrated AAL-5 SAR and DMA engine for data insertion and

extraction.

– Four classes of service.

– Integrated AAL-5-compliant and packet-based SAR.

– Programmable service rate.

– Programmable queue thresholds.

– Use of descriptors and DMA support for maximum perfor-

mance.

– 16-bit data bus transfer at up to 66 MHz.

◆

Algorithms implemented in hardware; software intervention

required for initialization and configuration only.

◆

Error protection on all external RAM and BIST on all internal

RAM.

◆

Inter-operable with the IDT ZTM200 traffic manager.

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.

1 of 29

2004 Integrated Device Technology, Inc.

*Notice: The information in this document is subject to change without notice

January 12, 2005

DSC 6797

IDT 89TTM553

89TTM55x Functional Block Diagram

Data Buffer Memory (DDR SDRAM)

89TTM552

Multicast

Engine (DFC)

SPI-4.2

Streaming

Interface

SIX-over-LVDS

Control Path SAR

(SAR)

CPU and Peripheral

Interface (CPIF, DMA)

ZBus

DSR,

BRX

Memory Controller

(PBC)

OQ Manager

(VOQM, BPQ)

Datapath

AAL-5

SAR (ILS)

DST,

BTX

SPI-4.2

Streaming

Interface

CSIX-over-LVD

Forwarding

and

Thresholding

Engine (AC)

Queue Manager

(QM)

Packet

Scheduler

(SS)

Statistics

Processor

(SP)

External

Statistics

Port

Extended Scheduler

Interface

89TTM553

89TTM552-to-89TTM553

Interface

Statistics

Processor

(SP)

Packet

Scheduler

(ARS, GS,

WFQ)

Forwarding

and

Thresholding

Engine (AC)

Queue Manager

(QM)

CPU and Peripheral

Interface (CPIF, DMA)

ZBus

2 of 29

*Notice: The information in this document is subject to change without notice

January 12, 2005

IDT 89TTM553

89TTM553 Pin Description

Note:

Information in this section is subject to change. Contact your IDT FAE before making design decisions.

In this data sheet, direction is indicated as follows: I for In, O for Out, B for Bi-directional, and P for power.

Signal Name

BLL_CLK_CP,

BLL_CLK_CN

I/O Type

1.5V HSTL Class 1

Dir.

Freq.

175 MHz

Remarks

BLL QDR SRAM input clock: This clock pair registers data

inputs on the rising edge of C and C#. All synchronous inputs

must meet setup and hold times around the clock rising

edges.

BLL QDR SRAM output clock: This clock pair times the control

outputs to the rising edge of K, and times the address and

data outputs to the rising edge of K and K#.

BLL QDR SRAM address outputs.

BLL QDR SRAM synchronous read output (active low): When

asserted, a read cycle is initiated to the external QDR SRAM

devices.

BLL QDR SRAM data inputs: Input data must meet setup and

hold times around the rising edges of C and C# during read

operations

BLL QDR SRAM synchronous write output (active low): When

asserted, a write cycle is initiated to the external QDR SRAM

devices.

BLL QDR SRAM write data outputs: Output data is synchro-

nized to the K and K# during write operations

HSTL reference. Nominally V

DDQ

/ 2, so connect to 0.75 V

BLL_CLK_KP,

BLL_CLK_KN

BLL_ADDR[21:0]

BLL_RD_N

1.5V HSTL Class 1

175 MHz

1.5V HSTL Class 1

175 MHz

BLL_DIN[17:0]

1.5V HSTL Class 1

175 MHz

BLL_WR_N

1.5V HSTL Class 1

175 MHz

BLL_DOUT[17:0]

BLL_VREF

1.5V HSTL Class 1

0.75V

—

175 MHz

—

Table 1 Buffer Linked List QDR SRAM

Signal Name

BXT_CLK_CP,

BXT_CLK_CN

I/O Type

1.5V HSTL Class 1

Dir.

Freq.

175 MHz

Remarks

BXT QDR SRAM input clock: This clock pair registers data

inputs on the rising edge of C and C#. All synchronous inputs

must meet setup and hold times around the clock rising

edges.

BXT QDR SRAM output clock: This clock pair times the con-

trol outputs to the rising edge of K, and times the address and

data outputs to the rising edge of K and K#.

BXT QDR SRAM address outputs.

BXT QDR SRAM synchronous read output (active low): When

asserted, a read cycle is initiated to the external QDR SRAM

devices.

BXT QDR SRAM data inputs: Input data must meet setup and

hold times around the rising edges of C and C# during read

operations

BXT_CLK_KP,

BXT_CLK_KN

BXT_ADDR[21:0]

BXT_RD_N

1.5V HSTL Class 1

175 MHz

1.5V HSTL Class 1

175 MHz

BXT_DIN[3:0]

1.5V HSTL Class 1

175 MHz

Table 2 Buffer Linked List Extension QDR SRAM (Part 1 of 2)

3 of 29

*Notice: The information in this document is subject to change without notice

January 12, 2005

IDT 89TTM553

Signal Name

BXT_WR_N

I/O Type

1.5V HSTL Class 1

Dir.

Freq.

175 MHz

Remarks

BXT QDR SRAM synchronous write output (active low): When

asserted, a write cycle is initiated to the external QDR SRAM

devices.

BXT QDR SRAM write data outputs: Output data is synchro-

nized to the K and K# during write operations

HSTL reference. Nominally V

DDQ

/ 2, so connect to 0.75 V

BXT_DOUT[3:0]

BXT_LLT_VREF

1.5V HSTL Class 1

0.75V

—

175 MHz

—

Table 2 Buffer Linked List Extension QDR SRAM (Part 2 of 2)

Signal Name

FCT_CLK_CP,

FCT_CLK_CN

I/O Type

1.5V HSTL Class 1

Dir.

Freq.

175 MHz

Remarks

FCT QDR SRAM input clock: This clock pair registers data

inputs on the rising edge of C and C#. All synchronous inputs

must meet setup and hold times around the clock rising

edges.

FCT QDR SRAM output clock: This clock pair times the con-

trol outputs to the rising edge of K, and times the address and

data outputs to the rising edge of K and K#.

FCT QDR SRAM address outputs.

FCT QDR SRAM synchronous read output (active low): When

asserted, a read cycle is initiated to the external QDR SRAM

devices.

FCT QDR SRAM data inputs: Input data must meet setup and

hold times around the rising edges of C and C# during read

operations

FCT QDR SRAM synchronous write output (active low): When

asserted, a write cycle is initiated to the external QDR SRAM

devices.

FCT QDR SRAM write data outputs: Output data is synchro-

nized to the K and K# during write operations

HSTL reference. Nominally V

DDQ

/ 2, so connect to 0.75 V

FCT_CLK_KP,

FCT_CLK_KN

FCT_ADDR[19:0]

FCT_RD_N

1.5V HSTL Class 1

175 MHz

1.5V HSTL Class 1

175 MHz

FCT_DIN[27:0]

1.5V HSTL Class 1

175 MHz

FCT_WR_N

1.5V HSTL Class 1

175 MHz

FCT_DOUT[27:0]

FCT_VREF[1:0]

1.5V HSTL Class 1

0.75

—

175 MHz

—

Table 3 Flow Control Table QDR SRAM

Signal Name

FPT_CLK_CP,

FPT_CLK_CN

I/O Type

1.5V HSTL Class 1

Dir.

Freq.

175 MHz

Remarks

FPT QDR SRAM input clock: This clock pair registers data

inputs on the rising edge of C and C#. All synchronous inputs

must meet setup and hold times around the clock rising

edges.

FPT QDR SRAM output clock: This clock pair times the con-

trol outputs to the rising edge of K, and times the address and

data outputs to the rising edge of K and K#.

FPT QDR SRAM address outputs.

FPT QDR SRAM synchronous read output (active low): When

asserted, a read cycle is initiated to the external QDR SRAM

devices.

FPT_CLK_KP,

FPT_CLK_KN

FPT_ADDR[20:0]

FPT_RD_N

1.5V HSTL Class 1

175 MHz

1.5V HSTL Class 1

175 MHz

Table 4 Flow Parameters Table QDR SRAM (Part 1 of 2)

4 of 29

*Notice: The information in this document is subject to change without notice

January 12, 2005

IDT 89TTM553

Signal Name

FPT_DIN[35:0]

I/O Type

1.5V HSTL Class 1

Dir.

Freq.

175 MHz

Remarks

FPT QDR SRAM data inputs: Input data must meet setup and

hold times around the rising edges of C and C# during read

operations

FPT QDR SRAM synchronous write output (active low): When

asserted, a write cycle is initiated to the external QDR SRAM

devices.

FPT QDR SRAM synchronous write byte enables (active low)

FPT QDR SRAM write data outputs: Output data is synchro-

nized to the K and K# during write operations

HSTL reference. Nominally V

DDQ

/ 2, so connect to 0.75 V

FPT_WR_N

1.5V HSTL Class 1

175 MHz

FPT_BW_N[3:0]

FPT_DOUT[35:0]

FPT_VREF[1:0]

1.5V HSTL Class 1

0.75V

—

175 MHz

—

Table 4 Flow Parameters Table QDR SRAM (Part 2 of 2)

Signal Name

GPT_CLK_CP,

GPT_CLK_CN

I/O Type

1.5V HSTL Class 1

Dir.

Freq.

175 MHz

Remarks

GPT QDR SRAM input clock: This clock pair registers data

inputs on the rising edge of C and C#. All synchronous inputs

must meet setup and hold times around the clock rising

edges.

GPT QDR SRAM output clock: This clock pair times the con-

trol outputs to the rising edge of K, and times the address and

data outputs to the rising edge of K and K#.

GPT QDR SRAM address outputs.

GPT QDR SRAM synchronous read output (active low): When

asserted, a read cycle is initiated to the external QDR SRAM

devices.

GPT QDR SRAM data inputs: Input data must meet setup and

hold times around the rising edges of C and C# during read

operations.

GPT QDR SRAM synchronous write output (active low): When

asserted, a write cycle is initiated to the external QDR SRAM

devices.

GPT QDR SRAM synchronous byte enables (active low).

GPT QDR SRAM write data outputs: Output data is synchro-

nized to the K and K# during write operations.

HSTL reference. Nominally V

DDQ

/ 2, so connect to 0.75 V

GPT_CLK_KP,

GPT_CLK_KN

GPT_ADDR[20:0]

GPT_RD_N

1.5V HSTL Class 1

175 MHz

1.5V HSTL Class 1

175 MHz

GPT_DIN[17:0]

1.5V HSTL Class 1

175 MHz

GPT_WR_N

1.5V HSTL Class 1

175 MHz

GPT_BW_N[1:0]

GPT_DOUT[17:0]

GPT_VREF

1.5V HSTL Class 1

0.75V

—

175 MHz

—

Table 5 Group Parameters Table QDR SRAM

5 of 29

*Notice: The information in this document is subject to change without notice

January 12, 2005

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Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

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