FemtoClock
®
NG Octal Universal
Frequency Translator
8T49N285
Datasheet
General Description
The 8T49N285 has a fractional-feedback PLL that can be used as a
jitter attenuator or frequency translator. It is equipped with six integer
and two fractional output dividers, allowing the generation of up to 8
different output frequencies, ranging from 8kHz to 1GHz. Three of
these frequencies are completely independent of each other and the
inputs. The other five are related frequencies. The eight outputs may
select among LVPECL, LVDS, HCSL or LVCMOS output levels.
This functionality makes it ideal to be used in any frequency
translation application, including 1G, 10G, 40G and 100G
Synchronous Ethernet, OTN, and SONET/SDH, including ITU-T
G.709 (2009) FEC rates. The device may also behave as a frequency
synthesizer.
The 8T49N285 accepts up to two differential or single-ended input
clocks and a crystal input. The PLL can lock to either input clock, but
both input clocks must be related in frequency.
The device supports hitless reference switching between input
clocks. The device monitors both input clocks for Loss of Signal
(LOS). It generates an alarm when an input clock failure is detected.
Automatic and manual hitless reference switching options are
supported. LOS behavior can be set to support gapped or un-gapped
clocks.
The 8T49N285 supports holdover with an initial accuracy of ±50ppB
from the point where the loss of all applicable input reference(s) has
been detected. It maintains a historical average operating point that
may be returned to in holdover at a limited phase slope.
The device places no constraints on input to output frequency
conversion, supporting all FEC rates, including the new revision of
ITU-T Recommendation G.709 (2009), most with 0ppm conversion
error.
The PLL has a register-selectable loop bandwidth from 1.4Hz to
360Hz.
Each output supports individual phase delay settings to allow
output-output alignment.
The device supports Output Enable inputs and Lock, Holdover and
LOS status outputs.
The device is programmable through an I
2
C interface. It also
supports I
2
C master capability to allow the register configuration to
be read from an external EEPROM.
Features
•
•
•
•
•
Supports SDH/SONET and Synchronous Ethernet clocks
including all FEC rate conversions
<0.3ps RMS typical jitter (including spurs),12kHz to 20MHz
Operating modes: locked to input signal, holdover and free-run
Initial holdover accuracy of ±50ppb
Accepts two LVPECL, LVDS, LVHSTL, HCSL or LVCMOS
input clocks
•
Accepts frequencies ranging from 8kHz up to 875MHz
•
Auto and manual input clock selection with hitless switching
•
Clock input monitoring, including support for gapped clocks
•
•
•
Phase-Slope Limiting and Fully Hitless Switching options to
control output phase transients
Operates from a 10MHz to 40MHz fundamental-mode crystal
Generates 8 LVPECL/LVDS/HCSL or 16 LVCMOS output clocks
•
Output frequencies ranging from 8kHz up to 1.0GHz (diff)
•
Output frequencies ranging from 8kHz to 250MHz (LVCMOS)
•
Four General Purpose I/O pins with optional support for status &
control:
•
Four Output Enable control inputs may be mapped to any of the
eight outputs
•
Lock, Holdover & Loss-of-Signal status outputs
•
•
•
•
•
•
Open-drain Interrupt pin
Nine programmable PLL loop bandwidth settings from 1.4Hz to
360Hz.
•
Optional Fast Lock function
Programmable output phase delays in steps as small as 16ps
Register programmable through I
2
C or via external I
2
C EEPROM
Bypass clock paths for system tests
Power supply modes
V
CC
/ V
CCA
/ V
CCO
3.3V / 3.3V / 3.3V
3.3V / 3.3V / 2.5V
3.3V / 3.3V / 1.8V (LVCMOS)
2.5V / 2.5V / 3.3V
2.5V / 2.5V / 2.5V
2.5V / 2.5V / 1.8V (LVCMOS)
-40°C to 85°C ambient operating temperature
Package: 56QFN, lead-free RoHs (6)
Applications
• OTN or SONET / SDH equipment Line cards (up to OC-192, and
supporting FEC ratios)
• OTN de-mapping (Gapped Clock and DCO mode)
• Gigabit and Terabit IP switches / routers including support of
Synchronous Ethernet
• SyncE (G.8262) applications
• Wireless base station baseband
• Data communications
• 100G Ethernet
•
•
©2016 Integrated Device Technology, Inc.
1
Revision 5, October 26, 2016
8T49N285 Datasheet
8T49N285 Block Diagram
XTAL
OSC
CLK0
CLK1
÷
P0
÷
P1
Input Clock
Monitoring,
Priority,
&
Selection
Fractional
Feedback
APLL
Lock
Holdover
IntN Output
Divider
IntN Output
Divider
FracN Output
Divider
FracN Output
Divider
Q0
Q1
Q2
Q3
IntN
nRST
Q4
Q5
Q6
Q7
Reset
Logic
I
2
C Master
LOS
Status Registers
Control Registers
4
IntN
GPIO
Logic
IntN
IntN
GPIO
nINT PLL_BYP
OTP
I
2
C Slave
SCLK
SDATA
Serial EEPROM
SA0
Figure 1. 8T49N285 Functional Block Diagram
©2016 Integrated Device Technology, Inc.
2
Revision 5, October 26, 2016
8T49N285 Datasheet
Pin Assignment
GPIO[2]
GPIO[3]
nQ2
Q2
V
CCO2
GPIO[0]
nQ3
Q3
V
CCO3
GPIO[1]
V
CCA
RESERVED
RESERVED
V
CC
V
CCA
V
CCA
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10 11 12 13 14
V
CCO4
V
CCO5
V
CCO6
V
CCO7
nQ4
nQ5
nQ6
nQ1
Q1
V
CCO1
nRST
nQ0
Q0
V
CCO0
nINT
V
CCA
CAP_REF
CAP
PLL_BYP
V
CCA
V
CCA
42 41 40 39 38 37 36 35 34 33 32 31 30 29
43
28
44
45
46
47
48
49
50
51
52
53
54
55
56
8T49N285
OSCO
SCLK
OSCI
S_A0
V
CCA
V
CCA
nQ7
Q4
Q5
Q6
Q7
SDATA
nCLK0
nCLK1
CLK0
56-pin, 8mm x 8mm VFQFN Package
Figure 2. Pin-out Drawing
©2016 Integrated Device Technology, Inc.
CLK1
V
CCA
V
CC
V
EE
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Revision 5, October 26, 2016
8T49N285 Datasheet
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
1
Number
3
4
5
12
13
7
8
9
10
48, 47
44, 43
27, 28
23, 24
40, 39
37, 36
34, 33
31, 30
46
Name
OSCI
OSCO
S_A0
SDATA
SCLK
CLK0
nCLK0
CLK1
nCLK1
Q0, nQ0
Q1, nQ1
Q2, nQ2
Q3, nQ3
Q4, nQ4
Q5, nQ5
Q6, nQ6
Q7, nQ7
nRST
I
O
I
I/O
I/O
I
I
I
I
O
O
O
O
O
O
O
O
I
Pulldown
Pullup
Pullup
Pulldown
Pullup /
Pulldown
Pulldown
Pullup /
Pulldown
Universal
Universal
Universal
Universal
Universal
Universal
Universal
Universal
Pullup
Open-drain
with pullup
Pullup
Pulldown
Type
Description
Crystal Input. Accepts a 10MHz-40MHz reference from a clock oscillator or
a 12pF fundamental mode, parallel-resonant crystal.
Crystal Output. This pin should be connected to a crystal. If an oscillator is
connected to OSCI, then this pin must be left unconnected.
I
2
C lower address bit A0.
I
2
C interface bi-directional Data.
I
2
C interface bi-directional Clock.
Non-inverting differential clock input.
Inverting differential clock input. V
CC
/2 when left floating (set by the internal
pullup and pulldown resistors.)
Non-inverting differential clock input.
Inverting differential clock input. V
CC
/2 when left floating (set by the internal
pullup and pulldown resistors.)
Output Clock 0. Please refer to the
“Output Drivers”
section for more details.
Output Clock 1. Please refer to the
“Output Drivers”
section for more details.
Output Clock 2. Please refer to the
“Output Drivers”
section for more details.
Output Clock 3. Please refer to the
“Output Drivers”
section for more details.
Output Clock 4. Please refer to the
“Output Drivers”
section for more details.
Output Clock 5. Please refer to the
“Output Drivers”
section for more details.
Output Clock 6. Please refer to the
“Output Drivers”
section for more details.
Output Clock 7. Please refer to the
“Output Drivers”
section for more details.
Master Reset input. LVTTL / LVCMOS interface levels.
0 = All registers and state machines are reset to their default values
1 = Device runs normally
Interrupt output.
General-purpose input-outputs. LVTTL / LVCMOS Input levels Open-drain
output.Pulled-up with 5.1k resistor to V
CC.
Bypass Selection. Allow input references to bypass the PLL.
LVTTL / LVCMOS interface levels
Negative supply voltage. All V
EE
pins and ePad must be connected before
any positive supply voltage is applied.
Core and digital functions supply voltage.
Core and digital functions supply voltage.
Analog functions supply voltage for core analog functions.
Analog functions supply voltage for analog functions associated with PLL.
High-speed output supply voltage for output pair Q0, nQ0.
High-speed output supply voltage for output pair Q1, nQ1.
High-speed output supply voltage for output pair Q2, nQ2.
High-speed output supply voltage for output pair Q3, nQ3.
High-speed output supply voltage for output pair Q4, nQ4.
50
29, 42, 21, 25
54
6, ePad
11
17
2, 14, 15, 16,
20
1, 51, 55, 56
49
45
26
22
41
nINT
GPIO[3:0]
PLL_BYP
V
EE
V
CC
V
CC
V
CCA
V
CCA
V
CCO0
V
CCO1
V
CCO2
V
CCO3
V
CCO4
O
I/O
I
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
©2016 Integrated Device Technology, Inc.
4
Revision 5, October 26, 2016
8T49N285 Datasheet
Table 1. Pin Descriptions
1
(Continued)
Number
38
35
32
53
52
18,
19
Name
V
CCO5
V
CCO6
V
CCO7
CAP,
CAP_REF
RESERVED
Power
Power
Power
Analog
Reserved
Type
Description
High-speed output supply voltage for output pair Q5, nQ5.
High-speed output supply voltage for output pair Q6, nQ6.
High-speed output supply voltage for output pair Q7, nQ7.
PLL External Capacitance.
Reserved pins.
NOTE 1:
Pullup
and
Pulldown
refer to internal input resistors. See
Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics, V
CC
= V
CCOX
= 3.3V±5% or 2.5V±5%
1
Symbol
C
IN
Parameter
Input Capacitance
2
Internal
Pullup
Resistor
nRST,
SDATA, SCLK
nINT
GPIO[3:0]
R
PULLDOWN
Internal Pulldown Resistor
LVCMOS
Q[0:1], Q[4:7]
LVCMOS Q[2:3]
LVCMOS
Q[0:1], Q[4:7]
Power
Dissipation
Capacitance
(per output
pair)
LVCMOS Q[2:3]
LVCMOS
Q[0:1], Q[4:7]
LVCMOS Q[2:3]
LVDS, HCSL or
LVPECL Q[0:1],
Q[4:7]
LVDS, HCSL or
LVPECL Q[2:3]
Output
Impedance
GPIO [3:0]
LVCMOS
Q[0:7], nQ[0:7]
V
CCOX
= 3.465V
V
CCOX
= 3.465V
V
CCOX
= 2.625V
V
CCOX
= 2.625V
V
CCOX
= 1.89V
V
CCOX
= 1.89V
V
CCOx
= 3.465V or 2.625V
V
CCOx
= 3.465V or 2.625V
Output HIGH
Output LOW
Test Conditions
Minimum
Typical
3.5
51
50
5.1
51
14.5
18.5
13
17.5
12.5
17
2
Maximum
Units
pF
k
k
k
k
pF
pF
pF
pF
pF
pF
pF
R
PULLUP
C
PD
4.5
5.1
25
20
pF
k
R
OUT
NOTE 1: V
CCOX
denotes: V
CCO0,
V
CCO1,
V
CCO2,
V
CCO3,
V
CCO4,
V
CCO5,
V
CCO6,
V
CCO7.
NOTE 2: This specification does not apply to OSCI and OSCO pins.
©2016 Integrated Device Technology, Inc.
5
Revision 5, October 26, 2016
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