9148F-11 datasheet, PDF - EEWORLD Datasheet

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9148F-11: DescriptionProcessor Specific Clock Generator, 33.3MHz, PDSO48, SSOP-48; CategoryThe embedded processor and controller Microcontrollers and processors; File Size581KB，14 Pages; ManufacturerIDT (Integrated Device Technology)

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9148F-11 Overview

Processor Specific Clock Generator, 33.3MHz, PDSO48, SSOP-48

9148F-11 Parametric

Parameter Name	Attribute value
Maker	IDT (Integrated Device Technology)
Parts packaging code	SSOP
package instruction	SSOP-48
Contacts	48
Reach Compliance Code	unknown
ECCN code	EAR99
JESD-30 code	R-PDSO-G48
length	15.875 mm
Number of terminals	48
Maximum operating temperature	70 °C
Minimum operating temperature
Maximum output clock frequency	33.3 MHz
Package body material	PLASTIC/EPOXY
encapsulated code	SSOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, SHRINK PITCH
Master clock/crystal nominal frequency	14.318 MHz
Maximum seat height	2.794 mm
Maximum supply voltage	3.465 V
Minimum supply voltage	3.135 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal pitch	0.635 mm
Terminal location	DUAL
width	7.5184 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, PROCESSOR SPECIFIC

9148F-11 Preview

Integrated

Circuit

Systems, Inc.

ICS9148-11

Frequency Generator & Integrated Buffers for PENTIUM

General Description

The

ICS9148-11

generates all clocks required for high speed RISC

or CISC microprocessor systems such as Intel PentiumPro. An

output enable pin is provided for testability. MODE allows power

management functions: CPU_STOP#, PCI_STOP# &

PWR_DWN#.

High drive BCLK outputs typically provide greater than 1V/ns slew

rate into 30 pF loads. PCLK outputs typically provide better than 1V/

ns slew rate into 20 pF loads while maintaining

50±

5% duty cycle.

The REF clock outputs typically provide better than 0.5V/ns slew

rates.

Features

Generates four processor, six bus, one 14.31818MHz and 12

SDRAM clocks.

Synchronous clocks skew matched to 250ps window on

CPU, SDRAM and 500ps window on BUS clocks.

CPUCLKs to BUS clocks skew 1-4 ns (CPU early)

Test clock mode eases system design

Custom configurations available

VDD(1:3) - 3.3V ±10%

(inputs 5V tolerant w/series R )

VDDL(1:2) - 2.5V or 3.3V ±5%

PC serial configuration interface

Power Management Control Input pins

48-pin SSOP package

Block Diagram

Pin Configuration

48-Pin SSOP

Functionality

CPUCLK,

SDRAM

(MHz)

High-Z

66.6

X1, REF

(MHz)

PCICLK

(MHz)

High-Z

14.318

High-Z

33.3

Pentium is a trademark of Intel Corporation

C is a trademark of Philips Corporation

9148-11 RevB 12/09/97P

ICS reserves the right to make changes in the device data identified in this

publication without further notice. ICS advises its customers to obtain the latest

version of all device data to verify that any information being relied upon by the

customer is current and accurate.

ICS9148-11

Pin Descriptions

PIN NUMBER

PIN NAME

TYPE

DESCRIPTION

3, 9, 16, 22, 27,

33, 39, 45

8, 10, 11, 12

13, 15

1, 6, 14,

19, 30, 36,

17, 18, 20, 21,

32, 34, 35, 37, 38

42, 48

40, 41, 43, 44

46, 47

REF0

GND

MODE

PCLK_F

PCICLK (0:5)

SDATA

SCLK

VDD1, VDD2,

VDD3

SDRAM

(0:4) (8:11)

VDDL2, VDDL1

CPUCLK (0:3)

IOAPIC (0:1)

SDRAM7

PCI_STOP#

SDRAM6

CPU_STOP#

SDRAM5

PWR_DWN#

OUT

PWR

OUT

PWR

OUT

PWR

OUT

14.318 MHz reference clock outputs.

Ground.

XTAL_IN 14.318MHz Crystal input, has internal 33pF load cap and feed

back resistor from X2

XTAL_OUT Crystal output, has internal load cap 33pF

Mode select pin for enabling power management features.

Free running BUS clock during PCI_STOP# = 0.

BUS clock outputs.

Logic input for output enable, tristates all outputs when low.

Serial data in for serial config port.

Clock input for serial config port.

Nominal 3.3V power supply, see power groups for function.

SDRAM clocks 66.6MHz.

CPU and IOAPIC clock power supply, either

2.5 or 3.3V nominal

CPU output clocks, powered by VDDL2 (66.6 MHz)

IOAPIC clock output, (14.318 MHz) powered by VDDL1

SDRAM clock 66.6 MHz selected

Halts PCICLK (0:5) at logic "0" level when low

SDRAM clock 66.6 MHz selected

Halts CPUCLK clocks at logic "0" level when low

SDRAM clock 66.6 MHz selected

Powers down chip, active low

Power Groups

VDD1 = REF0, X1, X2

VDD2 = PCICLK_F, PCICLK (0:5)

VDD3 = SDRAM (0:4) (8:11) SDRAM5/PWR_DWN#,

SDRAM6/CPU_STOP#, SDRAM7/PCI_STOP#, supply for PLL Core.

VDDL1 = IOAPIC (0:1)

VDDL2 = CPUCLK (0:3)

ICS9148-11

Power-On Conditions

MODE

PIN #

44, 43, 41, 40

38, 37, 35, 34,

32, 31, 21, 20,

18, 17, 29, 28

8, 10, 11,

12, 14, 15, 7

44, 43, 41, 40

38, 37, 35,

34, 32, 21,

20, 18, 17

8, 10, 11,

12, 14, 15

DESCRIPTION

CPUCLKs

SDRAM

PCICLKs

PCI_STOP#

CPU_STOP#

SDRAM/PWR

_DWN#

PCICLK_F

CPUCLKs

SDRAM

PCICLKs

FUNCTION

66.6 MHz - w/serial config enable/disable

66.6 MHz - All SDRAM outputs

33.3 MHz - w/serial config enable/disable

Power Management, PCI (0:5) Clocks Stopped

when low

Power Management, CPU (0:3) Clocks Stopped

when low

Used as PWR_DWN# when low

33.3 MHz - 33.3 MHz - PCI Clock Free running for

Power Management

66.6 MHz - CPU Clocks w/external Stop Control and

serial config individual enable/disable.

66.6 MHz - SDRAM Clocks w/serial config individual

enable/disable.

33.3 MHz - PCI Clocks w/external Stop control and

serial config individual enable/disable.

Example:

a) if MODE = 1, pins 28, 29 and 31 are configured as SDRAM7, SDRAM6 and SDRAM5 respectively.

b) if MODE = 0, pins 28, 29 and 31 are configured as PCI_STOP#, CPU_STOP# and PWR_DWN# respectively.

Power-On Default Conditions

At power-up and before device programming, all clocks will default to an enabled and on condition. The frequencies that are then

produced are on the FS and MODE pin as shown in the table below.

CLOCK

REF 0

IOAPIC (0:1)

DEFAULT CONDITION AT POWER-UP

14.31818 MHz

ICS9148-11

Technical Pin Function Descriptions

VDD(1,2,3)

This is the power supply to the internal core logic of the device as well

as the clock output buffers for REF(0:1), PCICLK, 48/24MHzA/B

and SDRAM(0:7).

This pin operates at 3.3V volts. Clocks from the listed buffers that it

supplies will have a voltage swing from Ground to this level. For the

actual guaranteed high and low voltage levels for the Clocks, please

consult the DC parameter table in this data sheet.

VDDL1,2

This is the power supplies for the CPUCLK and IOAPCI output

buffers. The voltage level for these outputs may be 2.5 or 3.3volts.

Clocks from the buffers that each supplies will have a voltage swing

from Ground to this level. For the actual Guaranteed high and low

voltage levels of these Clocks, please consult the DC parameter

table in this Data Sheet.

GND

This is the power supply ground (common or negative) return pin for

the internal core logic and all the output buffers.

This input pin serves one of two functions. When the device is used

with a Crystal, X1 acts as the input pin for the reference signal that

comes from the discrete crystal. When the device is driven by an

external clock signal, X1 is the device input pin for that reference

clock. This pin also implements an internal Crystal loading capacitor

that is connected to ground. With a nominal value fo 33pF no

external load cap is needed for a C

=17 to 18pF crystal.

This Output pin is used only when the device uses a Crystal as the

reference frequency source. In this mode of operation, X2 is an

output signal that drives (or excites) the discrete Crystal. The X2 pin

will also implement an internal Crystal loading capacitor nominally

33pF.

CPUCLK (0:3)

These Output pins are the Clock Outputs that drive processor and

other CPU related circuitry that requires clocks which are in tight

skew tolerance with the CPU clock. The voltage swing of these

Clocks are controlled by theVoltage level applied to theVDDL2 pin

of the device. See the Functionality Table for a list of the specific

frequencies that are available for these Clocks and the selection

codes to produce them.

SDRAM(0:11)

These Output Clocks are use to drive Dynamic RAMs and are low

skew copies of the CPU Clocks. The voltage swing of the

SDRAMs output is controlled by the supply voltage that is applied

to VDD3 of the device, operates at 3.3 volts.

IOAPIC (0:1)

This Output is a fixed frequency Output Clock that runs at the

Reference Input (typically 14.31818MHz) . Its voltage level swing

is controlled by VDDL1 and may operate at 2.5 or 3.3volts.

REF0

The REF Output is a fixed frequency Clock that runs at the same

frequency as the Input Reference Clock X1 or the Crystal (typically

14.31818MHz) attached across X1 and X2.

PCICLK_F

This Output is equal to PCICLK(0:5) and is FREE RUNNING, and

will not be stopped by PCI_STP#.

PCICLK (0:5)

These Output Clocks generate all the PCI timing requirements for a

Pentium/Pro based system. They conform to the current PCI

specification. They run at 1/2 CPU frequency.

MODE

This Input pin is used to select the Input function of the I/O pins. An

active Low will place the I/O pins in the Input mode and enable those

stop clock functions.

PWR_DWN#

This is an asynchronous active Low Input pin used to Power Down

the device into a Low Power state by not removing the power supply.

The internal Clocks are disabled and the VCO and Crystal are

stopped. Powered Down will also place all the Outputs in a low state

at the end of their current cycle. The latency of Power Down will not

be greater than 3ms. The I

C inputs will beTri-Stated and the device

will retain all programming information. This input pin only valid when

MODE=0 (Power Management Mode)

CPU_STOP#

This is a synchronous active Low Input pin used to stop the

CPUCLK clocks in an active low state. All other Clocks including

SDRAM clocks will continue to run while this function is enabled.

The CPUCLKs will have a turn ON latency of at least 3 CPU

clocks. This input pin only valid when MODE=0 (Power Management

Mode)

PCI_STOP#

This is a synchronous active Low Input pin used to stop the PCICLK

clocks in an active low state. It will not effect PCICLK_F nor any

other outputs. This input pin only valid when MODE=0 (Power

Management Mode)

The SDATA and SCLOCK Inputs are use to program the device.

The clock generator is a slave-receiver device in the I

C protocol.

It will allow read-back of the registers. See configuration map for

C specification in Philips I

C Peripherals

Data Handbook (1996) should be followed.

Output Enable tristates the outputs when held low. This pin will

override the I

C Byte 0 function, so that the outputs will be tristated

when the OE is low regardless of the I

C defined function. When OE

is high, the I

C function is in active control.

ICS9148-11

General I

C serial interface information

For the clock generator to be addressed by an I

C controller, the following address must be sent as a start sequence,

with an acknowledge bit between each byte.

Clock Generator

Address (7 bits)

A(6:0) & R/W#

(H)

ACK

+ 8 bits dummy

command code

ACK

+ 8 bits dummy

Byte count

ACK

Then Byte 0, 1, 2, etc in

sequence until STOP.

The clock generator is a slave/receiver I

C component. It can "read back "(in Philips I

C protocol) the data stored in the

latches for verification. (set R/W# to 1 above). There is no BYTE count supported, so it does not meet the Intel SMB

PIIX4 protocol.

Clock Generator

Address (7 bits)

A(6:0) & R/W#

(H)

ACK

Byte 0

ACK

Byte 1

ACK

Byte 0, 1, 2, etc in sequence until STOP.

The data transfer rate supported by this clock generator is 100K bits/sec (standard mode)

The input is operating at 3.3V logic levels.

The data byte format is 8 bit bytes.

To simplify the clock generator I

C interface, the protocol is set to use only block writes from the controller. The bytes

must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has

been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two

bytes. The data is loaded until a Stop sequence is issued.

In the power down mode (PWR_DWN# Low), the SDATA and SCLK pins are tristated and the internal data latches

maintain all prior programming information.

At power-on, all registers are set to a default condition. See Byte 0 detail for default condition, Bytes 1 through 5 default

to a 1 (Enabled output state)

Serial Configuration Command Bitmaps

Byte 0: Functional and Frequency Select Clock Register (Default=0)

BIT

Bit 7

Bit 6

PIN#

DESCRIPTION

Bit 5

Bit 4

Bit

Reserved

Must be 0 for normal operation

In Spread Spectrum, Controls type

(0=centered, 1=down spread)

Must be 0 for normal operation

In Spread Spectrum, Controls Spreading

(0=1.8%, 1=0.6%)

Reserved

Bit1

Bit0

1 - Tri-State

0 - Spread Spectrum Enable

1 - Testmode

0 - Normal operation

PWD

Note:

PWD = Power-Up Default

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