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Datasheet> All Categories > The embedded processor and controller> Microcontrollers and processors> 952906BGLFT
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952906BGLFT

Description
TSSOP-48, Reel
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size465KB，24 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance  
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952906BGLFT Overview

TSSOP-48, Reel

952906BGLFT Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeTSSOP
Contacts48
Manufacturer packaging codePAG48
Reach Compliance Codecompliant
ECCN codeEAR99
Samacsys DescriptionTSSOP 6.1 MM 0.5MM PITCH
JESD-609 codee3
Humidity sensitivity level1
Peak Reflow Temperature (Celsius)260
technologyCMOS
Terminal surfaceMATTE TIN
Maximum time at peak reflow temperatureNOT SPECIFIED
uPs/uCs/peripheral integrated circuit typeCLOCK GENERATOR, PROCESSOR SPECIFIC

952906BGLFT Preview

Integrated
Circuit
Systems, Inc.
ICS952906A
Programmable Timing Control Hub™ for Next Gen P4™ processor
Recommended Application:
VIA VN800/CN700/P4M800 style chipset for P4 processor
Output Features:
•
3 - 0.7V current-mode differential CPU pairs
•
10 - PCI, 3 free running, 33MHz
•
2 - REF, 14.318MHz
•
3 - 3V66, 66.66MHz
•
1 - 48MHz
•
1 - 24/48MHz
•
2 - 25MHz @ 2.5V
Key Specifications:
•
CPU/SRC outputs cycle-cycle jitter < 125ps
•
3V66 outputs cycle-cycle jitter < 250ps
•
PCI outputs cycle-cycle jitter < 250ps
•
CPU - AGP skew < +/- 350ps
•
AGP-PCI skew between 1~3.5ns
Functionality
Bit4 Bit3 Bit2 Bit1 Bit0 CPU
FS4 FS3 FS2 FS1 FS0 MHz
100.00
0
0
0
0
0
200.00
0
0
0
0
1
133.33
0
0
0
1
0
166.67
0
0
0
1
1
0
0
1
0
0
200.00
0
0
1
0
1
400.00
0
0
1
1
0
266.67
0
0
1
1
1
333.33
100.99
0
1
0
0
0
201.98
0
1
0
0
1
134.65
0
1
0
1
0
168.31
0
1
0
1
1
1
115.00
0
1
0
0
230.00
0
1
1
0
1
153.33
0
1
1
1
0
191.67
0
1
1
1
1
1
100.00
0
0
0
0
200.00
1
0
0
0
1
133.33
1
0
0
1
0
166.67
1
0
0
1
1
0
1
0
0
200.00
1
400.00
1
0
1
0
1
266.67
1
0
1
1
0
333.33
1
0
1
1
1
105.00
1
1
0
0
0
210.00
1
1
0
0
1
140.00
1
1
0
1
0
175.00
1
1
0
1
1
1
110.00
1
1
0
0
220.00
1
1
1
0
1
146.66
1
1
1
1
0
1
1
1
1
1
183.34
1236A—08/06/07
Features/Benefits:
•
Programmable output frequency.
•
Programmable asynchronous 3V66&PCI frequency.
•
Programmable output divider ratios.
•
Programmable output skew.
•
Programmable spread percentage for EMI control.
•
Watchdog timer technology to reset system if system
malfunctions.
•
Programmable watch dog safe frequency.
•
Support I2C Index read/write and block read/write
operations.
•
Uses external 14.318MHz reference input.
Pin Configuration
AGP
MHz
66.67
66.67
66.67
66.67
66.67
66.67
66.67
66.67
67.33
67.33
67.33
67.32
76.67
76.67
76.66
76.67
66.66
66.66
66.66
71.43
66.66
66.66
66.66
66.66
69.99
69.99
69.99
69.99
73.33
73.33
73.33
73.33
PCI
MHz
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.66
33.66
33.66
33.66
38.33
38.33
38.33
38.33
33.33
33.33
33.33
35.71
33.33
33.33
33.33
33.33
35.00
35.00
35.00
35.00
36.66
36.66
36.66
36.66
*FS1/REF0
**FS0/REF1
VDDREF
X1
X2
GND
**FS2/PCICLK_F0
**FS4/PCICLK_F1
PCICLK_F2
VDDPCI
GND
**MODE/PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDDPCI
GND
PCICLK5
PCICLK6
**FS3/48MHz
**Sel24_48#/24_48MHz
GND
VDD48
* This
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDA
GND
IREF
CPUCLKT_ITP/(PCI_STOP#)
CPUCLKC_ITP/(CPU_STOP#)
GND
CPUCLKT1
CPUCLKC1
VDDCPU
CPUCLKT0
CPUCLKC0
GND
25Mhz_0
25Mhz_1
VDD2.5
VttPWR_GD/PD#
SDATA
SCLK
Reset#
3V66_0
GND
VDD3V66
3V66_1
3V66_2
pin have 120K pull-up to VDD
** This pin have 120K pull-down to GND
48-pin SSOP & TSSOP
ICS952906
Integrated
Circuit
Systems, Inc.
ICS952906A
Pin Description
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
PIN NAME
*FS1/REF0
**FS0/REF1
VDDREF
X1
X2
GND
**FS2/PCICLK_F0
**FS4/PCICLK_F1
PCICLK_F2
VDDPCI
GND
**MODE/PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDDPCI
GND
PCICLK5
PCICLK6
**FS3/48MHz
**Sel24_48#/24_48MHz
GND
VDD48
3V66_2
3V66_1
VDD3V66
GND
3V66_0
Reset#
SCLK
SDATA
VttPWR_GD/PD#
VDD2.5
25Mhz_1
25Mhz_0
GND
CPUCLKC0
CPUCLKT0
VDDCPU
CPUCLKC1
CPUCLKT1
GND
PIN TYPE DESCRIPTION
I/O
Frequency select latch input pin / 14.318 MHz reference clock.
I/O
Frequency select latch input pin / 14.318 MHz reference clock.
PWR
Ref, XTAL power supply, nominal 3.3V
IN
Crystal input, Nominally 14.318MHz.
OUT
Crystal output, Nominally 14.318MHz
PWR
Ground pin.
I/O
Frequency select latch input pin / 3.3V PCI free running clock output.
I/O
Frequency select latch input pin / 3.3V PCI free running clock output.
OUT
Free running PCI clock not affected by PCI_STOP# .
PWR
Power supply for PCI clocks, nominal 3.3V
PWR
Ground pin.
Function select latch input pin, 0=Desktop Mode (pin 44/45 are outputs), 1=Mobile Mode (pin44/45 are STOP
I/O
inputs) / PCI clock output.
OUT
PCI clock output.
OUT
PCI clock output.
OUT
PCI clock output.
OUT
PCI clock output.
PWR
Power supply for PCI clocks, nominal 3.3V
PWR
Ground pin.
OUT
PCI clock output.
OUT
PCI clock output.
I/O
Frequency select latch input pin / Fixed 48MHz clock output. 3.3V
I/O
PWR
PWR
OUT
OUT
PWR
PWR
OUT
OUT
IN
I/O
IN
PWR
OUT
OUT
PWR
OUT
OUT
PWR
OUT
OUT
PWR
Latched select input for 24/48MHz output / 24/48MHz clock output. 1=24MHz, 0 = 48MHz.
Ground pin.
Power pin for the 48MHz output.3.3V
3.3V 66.66MHz clock output
3.3V 66.66MHz clock output
Power pin for the 3.3V 66MHz clocks.
Ground pin.
3.3V 66.66MHz clock output
Real time system reset signal for frequency gear ratio change or watchdog timer timeout. This signal is
active low.
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 3.3V tolerant.
This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs are valid and are ready
to be sampled. This is an active high input. / Asynchronous active low input pin used to power down the
device into a low power state.
Power supply, nominal 2.5V
25MHz clock output, 2.5V
25MHz clock output, 2.5V
Ground pin.
Complementary clock of differential pair CPU outputs. These are current mode outputs. External resistors
are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required
for voltage bias.
Supply for CPU clocks, 3.3V nominal
Complementary clock of differential pair CPU outputs. These are current mode outputs. External resistors
are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required
for voltage bias.
Ground pin.
Complementary clock of differential pair CPU outputs. These are current mode outputs. External resistors
are required for voltage bias. / Stops all CPUCLK besides the free running clocks
True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required
for voltage bias. / Stops all PCICLK besides the free running clocks
This pin establishes the reference current for the differential current-mode output pairs. This pin requires a
fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard
value.
Ground pin.
3.3V power for the PLL core.
CPUCLKC_ITP/(CPU_STOP#) I/O
CPUCLKT_ITP/(PCI_STOP#)
I/O
46
47
48
IREF
GND
VDDA
OUT
PWR
PWR
1236A—08/06/07
2
Integrated
Circuit
Systems, Inc.
ICS952906A
General Description
ICS952906A
is a 48 pin clock chip for VIA VN800/CN700/P4M800 style chipsets. When used with a fanout DDR buffer, such
as the 93788, it provides all the necessary clock signals for such a system.
The
ICS952906A
is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). This part
incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a
serially programmable I
2
C interface, this device can adjust the output clocks by configuring the frequency setting, the output
divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each
individual output clock. M/N control can configure output frequency with resolution up to 0.1MHz increment.
Block Diagram
PLL2
Frequency
Dividers
48MHz
24_48MHz
X1
X2
XTAL
REF (1:0)
CPUCLKT (1:0)/ITP
CPU_STOP#
PCI_STOP#
FS (4:0)
SCLK
Sel24_48#
SDATA
MODE
VTTPWRGD#/PD#
PCICLK_F (2:0)
RESET#
I REF
Control
Logic
Programmable
Spread
PLL1
Programmable
Frequency
Dividers
STOP
Logic
CPUCLKC (1:0)/ITP
25MHz (1:0)
3V66 (2:0)
PCICLK (6:0)
Power Groups
Pin Number
VDD
GND
3
6
10, 17
11, 18
24
23
27
28
34
37
40
43
48
47
Description
REF, Xtal
PCICLK outputs
48MHz Fix, Fix Digital, Fix analog
3V66 outputs
2.5V for 25MHz outputs
CPU outputs
CPU Analog, CPU digital
1236A—08/06/07
3
Integrated
Circuit
Systems, Inc.
ICS952906A
General I
2
C serial interface information for the ICS952906A
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte location = N
ICS clock will
acknowledge
Controller (host) sends the data byte count = X
ICS clock will
acknowledge
Controller (host) starts sending
Byte N through
Byte N + X -1
(see Note 2)
• ICS clock will
acknowledge
each byte
one at a time
• Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
How to Read:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) will send start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will
acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3
(H)
ICS clock will
acknowledge
ICS clock will send the data byte count = X
ICS clock sends
Byte N + X -1
ICS clock sends
Byte 0 through byte X (if X
(H)
was written to byte 8)
.
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host)
starT bit
T
Slave Address D2
(H)
WR
WRite
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ICS (Slave/Receiver)
Index Block Read Operation
Controller (Host)
T
starT bit
Slave Address D2
(H)
WR
WRite
Beginning Byte = N
ACK
RT
Repeat starT
Slave Address D3
(H)
RD
ReaD
ACK
Data Byte Count = X
ACK
Beginning Byte N
X Byte
ICS (Slave/Receiver)
ACK
ACK
Byte N + X - 1
ACK
P
stoP bit
ACK
Byte N + X - 1
N
P
1236A—08/06/07
Not acknowledge
stoP bit
4
Integrated
Circuit
Systems, Inc.
ICS952906A
Table1: QuadRom Frequency Selection Table
Bit6 Bit5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit4 Bit3 Bit2 Bit1 Bit0
FS4 FS3 FS2 FS1 FS0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CPU
MHz
100.00
200.00
133.33
166.67
200.00
400.00
266.67
333.33
100.99
201.98
134.65
168.31
115.00
230.00
153.33
191.67
100.00
200.00
133.33
166.67
200.00
400.00
266.67
333.33
105.00
210.00
140.00
175.00
110.00
220.00
146.66
183.34
AGP
MHz
66.67
66.67
66.67
66.67
66.67
66.67
66.67
66.67
67.33
67.33
67.33
67.32
76.67
76.67
76.66
76.67
66.66
66.66
66.66
71.43
66.66
66.66
66.66
66.66
69.99
69.99
69.99
69.99
73.33
73.33
73.33
73.33
PCI
MHz
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.66
33.66
33.66
33.66
38.33
38.33
38.33
38.33
33.33
33.33
33.33
35.71
33.33
33.33
33.33
33.33
35.00
35.00
35.00
35.00
36.66
36.66
36.66
36.66
Spread
%
0 to -0.5% Down
0 to -0.5% Down
0 to -0.5% Down
0 to -0.5% Down
0 to -0.5% Down
0 to -0.5% Down
0 to -0.5% Down
0 to -0.5% Down
0.25% Center
0.25% Center
0.25% Center
0.25% Center
No Spread
No Spread
No Spread
No Spread
0.25% Center
0.25% Center
0.25% Center
0.25% Center
0.25% Center
0.25% Center
0.25% Center
0.25% Center
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
1236A—08/06/07
5
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952906BGLFT Related Products

952906BGLFT 952906AFLF 952906BFLFT
Description TSSOP-48, Reel SSOP-48, Tube SSOP-48, Reel
Brand Name Integrated Device Technology Integrated Device Technology Integrated Device Technology
Is it lead-free? Lead free Lead free Lead free
Is it Rohs certified? conform to conform to conform to
Maker IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology)
Parts packaging code TSSOP SSOP SSOP
Contacts 48 48 48
Manufacturer packaging code PAG48 PVG48 PVG48
Reach Compliance Code compliant compliant compli
ECCN code EAR99 EAR99 EAR99
JESD-609 code e3 e3 e3
Humidity sensitivity level 1 1 1
Peak Reflow Temperature (Celsius) 260 260 260
technology CMOS CMOS CMOS
Terminal surface MATTE TIN MATTE TIN Matte Tin (Sn)
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
uPs/uCs/peripheral integrated circuit type CLOCK GENERATOR, PROCESSOR SPECIFIC CLOCK GENERATOR, PROCESSOR SPECIFIC CLOCK GENERATOR, PROCESSOR SPECIFIC

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  7. Semiconductor equipment orders increase, Jingsheng Electromechanical's net profit in 2021 is expected to increase by 114%
  8. The use of 51 single chip microcomputer serial port and serial communication
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Technical ResourceMore

  1. Intelligent Motor Controller UMC22-FBP Product Introduction
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  3. C Programming Tutorial - Use in Class
  4. China Power Industry Yearbook
  5. Littelfuse Ethernet Electrical Threats and Protection Solutions
  6. Analog-to-Digital Converter AD7746 Example Code
  7. C language example analysis essence_Cao Yanlong
  8. Numerical calculations of heat transfer and fluid flow
  9. Introduction to Switching Power Supply Design and Example Analysis
  10. WTK 2.5 official version

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