a single-chip four-host PCI-to-Universal Serial Bus
(USB) solution. The USS-344 interfaces directly to any
32-bit, 33 MHz PCI bus and is ideal for either onboard
applications or add-in card applications. It can easily be
configured to communicate in either a 3 V PCI environ-
ment or 5 V PCI environment simply by selecting the
appropriate communications voltage level on the VIO
input pin.
The USS-344 provides four downstream USB ports for
connectivity with any USB compliant device or hub. Full-
speed or low-speed peripherals are supported along
with all of the USB transfer types: control, interrupt,
bulk, or isochronous. The USS-344’s OpenHCI compli-
ance offers significant USB performance benefits and
reduced CPU overhead compared to other USB UHCI
host controllers.
In addition, the USS-344 offers a significant perfor-
mance advantage over all other USB host controllers
(both UHCI and OHCI) by providing full USB bandwidth
to each port rather than sharing the USB bandwidth
over all ports. This results in an increase in the number
of devices which can feasibly be connected to a
computer system as well as ensuring high-bandwidth
devices, such as video cameras and audio devices, are
always provided with the high bandwidth they need
while other USB devices are in use.
The USS-344 is a multifunction PCI device with one
single-port USB host controller per PCI function. There
are four PCI functions in the USS-344 for a total of four
single-port USB host controllers. Each single-port host
controller provides the full USB bandwidth (12 Mbits/s)
for devices connected downstream of its port.
The USS-344 is fully compatible with the
Microsoft
Windows
standard OpenHCI drivers. The USS-344
pinout is compatible with the future release of the Agere
USB 2.0 host controller.The USS-344 is a 3.3 V device
fabricated in 0.25
µm
technology. Integrated dual-speed
USB transceivers enable a single-chip PCI-to-USB
solution. The USS-344 provides full support for legacy
PC peripherals as defined in the
OpenHCI Open Host
Controller Interface Specification for USB Release 1.0a.
*
Microsoft, Windows,
and
Windows NT
are registered trademarks
of Microsoft Corporation.
†
Mac
is a registered trademark of Apple Computer, Inc.
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32-bit, 33 MHz PCI interface compliant with
PCI Local
Bus Specification Revision 2.2
Four downstream USB ports
Each USB port dedicated to providing full USB band-
width to the attached device
Full compliance with
Universal Serial Bus Specifica-
tion Revision 1.1
OpenHCI Open Host Controller Interface Specifica-
tion for USB Release 1.0a
compatible
Fully compatible with
Microsoft Windows
98/95/Win-
dows NT
* standard OpenHCI drivers
Fully compatible with
Mac
†
OS 8.5 and 8.6
Integrated dual-speed USB transceivers
3 V or 5 V switchable PCI signaling
Low-power mode and wake-up compatible with
PCI
Power Management Interface Specification Revision
1.1
Supports up to 127 devices per port
Supports peripheral hot swap and wake-up
Support for legacy keyboard and mouse
128-pin TQFP package
Full 12 Mbits/s bandwidth per port
Evaluation kit:
— PCI card
— Data sheet
0.25
µm
technology
Applications
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Seamless integration with 3 V or 5 V PCI-based com-
puter products
Supports all USB compliant devices and hubs
Simultaneous operation of multiple high-performance
devices
USS-344
QuadraBus
Four-Host PCI-to-USB OpenHCI Host Controller
Advance Data Sheet, Rev. 9
June 2001
Table of Contents
Contents
Page
Features .................................................................................................................................................................. 1
Applicable Documents and Specifications ............................................................................................................... 4
Pin Information ........................................................................................................................................................ 4
PCI Function 0—Single-Port USB Host Controller 0 .......................................................................................12
PCI Function 1—Single-Port USB Host Controller 1 .......................................................................................16
PCI Function 2—Single-Port USB Host Controller 2 .......................................................................................20
PCI Function 3—Single-Port USB Host Controller 3 .......................................................................................24
USB Registers ....................................................................................................................................................... 28
Legacy Support Registers ..................................................................................................................................... 35
USB Connection Instructions...........................................................................................................................38
Test Mode Connection Instructions .................................................................................................................38
Power Connection Recommendations .................................................................................................................. 41
Power Management Interface ............................................................................................................................... 42
Configuration Space Offset 50h.......................................................................................................................43
Configuration Space Offset 51h.......................................................................................................................43
Configuration Space Offset 52h.......................................................................................................................44
Configuration Space Offset 54h.......................................................................................................................44
Configuration Space Offset 56h.......................................................................................................................45
Configuration Space Offset 57h.......................................................................................................................45
Power Consumption/Dissipation Reporting .....................................................................................................45
NAND Tree Mode .................................................................................................................................................. 46
Absolute Maximum Ratings ................................................................................................................................... 48
USB Electrical Characteristics .........................................................................................................................52
Ordering Information .............................................................................................................................................. 54
2
Agere Systems Inc.
Advance Data Sheet, Rev. 9
June 2001
USS-344
QuadraBus
Four-Host PCI-to-USB OpenHCI Host Controller
Description
(continued)
USS-344 PCI-TO-USB OpenHCI HOST CONTROLLER
ADDRESS
DATA
CONTROL
HCI
SLAVE
BLOCK
USB
STATE
CONTROL
ROOT
HUB
AND
HOST
SIE
TX
OHCI
ROOT
HUB
PORT
1
DATA
ADDRESS/
DATA
CONTROL
HCI
MASTER
BLOCK
LIST
PROCESSOR
BLOCK
HSIE
S/M
FIFO
DPLL
RX
MIRQ121
KIRQ1I
A20I
IRQ1
IRQ12
A20MN
SMIN
CLK48STOP
PMEN
LEGACY
SUPPORT
POWER
MNGMNT
LOGIC
POWER
MNGMNT
PCI CORE 0
LEGACY
LOGIC
USB HOST CONTROLLER
CORE 0
USB
AD[31:0]
CBE[3:0]
REQN
GNTN
IDSEL
FRAMEN
IRDYN
TRDYN
DEVSELN
STOPN
PERRN
SERRN
PAR
INTA
INTB
INTC
INTD
POWER
MNGMNT
PCI
ARBITER
PCI CORE 1
LEGACY
LOGIC
USB HOST CONTROLLER
CORE 1
USB
PCI BUS
POWER
MNGMNT
PCI CORE 2
LEGACY
LOGIC
USB HOST CONTROLLER
CORE 2
USB
POWER
MNGMNT
PCI CORE 3
LEGACY
LOGIC
USB HOST CONTROLLER
CORE 3
USB
5-7828.r1
Figure 1. USS-344 Interconnection Diagram
Agere Systems Inc.
3
USS-344
QuadraBus
Four-Host PCI-to-USB OpenHCI Host Controller
Advance Data Sheet, Rev. 9
June 2001
Applicable Documents and Specifications
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PCI Local Bus Specification Revision 2.1s.,
June 1, 1995. PCI Special Interest Group.
Universal Serial Bus Specification Revision 1.1.,
September 23, 1998. Compaq/Digital Equipment Corporation/
IBM PC Company/Intel/Microsoft/NEC/Northern Telecom.
OpenHCI Open Host Controller Interface Specification for USB Release 1.0a.,
July 31, 1997. Compaq/Microsoft/
National Semiconductor.
PCI Bus Power Management Interface Specification Revision 1.1.,
December 18, 1998. PCI Special Interest
Group.
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Pin Information
AD25
AD26
AD27
AD28
VDD
VSS
AD29
AD30
AD31
PMEN
VDD
VSS
REQN
GNTN
VSS
CLK
VDD
RSTN
INTDN
INTCN
INTBN
VSS
VDD
INTAN
PWRFLT3N
PRTPWR3
VDD
VSS
AD24
C/BEN3
IDSEL
AD23
AD22
VSS
VDD
AD21
AD20
AD19
AD18
VSS
VDD
AD17
AD16
C/BEN2
FRAMEN
VDD
VSS
IRDYN
TRDYN
DEVSELN
STOPN
PERRN
VSS
VDD
SERRN
PAR
C/BEN1
AD15
VDD
VSS
AD14
AD13
AD12
AD11
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
USS-344
PWRFLT2N
PRTPWR2
VSST
VDDT
DMNS3
DPLS3
DMNS2
DPLS2
VSST
VDDT
DMNS1
DPLS1
DMNS0
DPLS0
VSST
VDDT
RREF
VDDA
XHI
XLO/CLK48
VSSA
CLK48STOP
VDD
PWRFLT1N
PRTPWR1
PWRFLT0N
PRTPWR0
SMIN
VSS
VDD
IRQ12
IRQ1
A20MN
A20I
KIRQ1I
MIRQ12I
VSS
VDD
VDD
VSS
AD10
AD9
AD8
C/BEN0
VSS
VDD
AD7
AD6
AD5
AD4
VSS
VDD
AD3
AD2
AD1
AD0
VSS
VIO
VDD
VSS
TEST0
TEST1
TEST2
TEST3
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
5-7830
Figure 2. USS-344 Pin Diagram
4
Agere Systems Inc.
Advance Data Sheet, Rev. 9
June 2001
USS-344
QuadraBus
Four-Host PCI-to-USB OpenHCI Host Controller
Pin Information
(continued)
Table 1. Numeric Pin Cross Reference
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Symbol*
V
DD
V
SS
AD24
C/BEN3
IDSEL
AD23
AD22
V
SS
V
DD
AD21
AD20
AD19
AD18
V
SS
V
DD
AD17
AD16
C/BEN2
FRAMEN
V
DD
V
SS
IRDYN
TRDYN
DEVSELN
STOPN
PERRN
V
SS
V
DD
SERRN
PAR
C/BEN1
AD15
Pin
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Symbol*
V
DD
V
SS
AD14
AD13
AD12
AD11
V
DD
V
SS
AD10
AD9
AD8
C/BEN0
V
SS
V
DD
AD7
AD6
AD5
AD4
V
SS
V
DD
AD3
AD2
AD1
AD0
V
SS
VIO
V
DD
V
SS
TEST0
TEST1
TEST2
TEST3
Pin
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
Symbol*
V
DD
V
SS
MIRQ12I
KIRQ1I
A20I
A20MN
IRQ1
IRQ12
V
DD
V
SS
SMIN
PRTPWR0
PWRFLT0N
PRTPWR1
PWRFLT1N
V
DD
CLK48STOP
V
SS
A
XLO/CLK48
XHI
V
DD
A
RREF
V
DD
T
V
SS
T
DPLS0
DMNS0
DPLS1
DMNS1
V
DD
T
V
SS
T
DPLS2
DMNS2
Pin
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
Symbol*
DPLS3
DMNS3
V
DD
T
V
SS
T
PRTPWR2
PWRFLT2N
PRTPWR3
PWRFLT3N
INTAN
V
DD
V
SS
INTBN
INTCN
INTDN
RSTN
V
DD
CLK
V
SS
GNTN
REQN
V
SS
V
DD
PMEN
AD31
AD30
AD29
V
SS
V
DD
AD28
AD27
AD26
AD25
* Pins identified as NC are unused and should be left unconnected. Active-low signals within this document are indicated by an N following the
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