32 Megabit (1M x 32-Bit), 16 Megabit (512K x 32-Bit)
2.5 Volt-only Burst Mode, Dual Boot,
Simultaneous Read/Write Flash Memory
with VersatileI/O™ featuring 170 nm Process Technology
Data Sheet
(Preliminary)
Distinctive Characteristics
Architecture Advantages
Simultaneous Read/Write Operations
– Read data from one bank while executing erase/program functions
in other bank
– Zero latency between read and write operations
– Two bank architecture: large bank/small bank 75% / 25%
– Standby mode: CMOS: 60 µA max
1 million write cycles per sector typical
20 year data retention typical
VersatileI/O™ Control
– Generates data output voltages and tolerates data input voltages as
determined by the voltage on the V
IO
pin
– 1.65 V to 3.60 V compatible I/O signals
User-Defined x32 Data Bus
Dual Boot Block
– Top and bottom boot sectors in the same device
Software Features
Persistent Sector Protection
– Locks combinations of individual sectors and sector groups to
prevent program or erase operations within that sector (requires
only V
CC
levels)
Flexible Sector Architecture
– CD032G: Eight 2K Double Word, Sixty-two 16K Double Word, and
Eight 2K Double Word sectors
– CD016G: Eight 2K Double Word, Thirty-two 16K Double Word, and
Eight 2K Double Word sectors
Password Sector Protection
– Locks combinations of individual sectors and sector groups to
prevent program or erase operations within that sector using a user-
definable 64-bit password
Secured Silicon Sector (256 Bytes)
–
Factory locked and identifiable:
16 bytes for secure, random factory
Electronic Serial Number; Also know as Electronic Marking
Manufactured on 170 nm Process Technology
Programmable Burst Interface
– Interfaces to any high performance processor
– Linear Burst Read Operation: 2, 4, and 8 double word linear burst
with or without wrap around
Supports Common Flash Interface (CFI)
Unlock Bypass Program Command
– Reduces overall programming time when issuing multiple program
command sequences
Data# Polling and Toggle Bits
– Provides a software method of detecting program or erase operation
completion
Program Operation
– Performs synchronous and asynchronous write operations of burst
configuration register settings independently
Single Power Supply Operation
– Optimized for 2.5 to 2.75 volt read, erase, and program operations
Hardware Features
Program Suspend/Resume & Erase Suspend/Resume
– Suspends program or erase operations to allow reading,
programming, or erasing in same bank
Compatibility with JEDEC standards (JC42.4)
– Software compatible with single-power supply Flash
– Backward-compatible with AMD/Fujitsu Am29LV/MBM29LV and
Am29F/MBM29F flash memories
Hardware Reset (RESET#), Ready/Busy# (RY/BY#), and Write
Protect (WP#) Inputs
ACC Input
– Accelerates programming time for higher throughput during system
production
Performance Characteristics
High Performance Read Access
– Initial/random access times of 48 ns (32 Mb) and 54 ns (16 Mb)
– Burst access times of 7.5 ns (32 Mb) or 9 ns (16Mb)
Package Options
–
–
–
–
80-pin PQFP
80-ball Fortified BGA
Pb-free package option also available
Known Good Die
Ultra Low Power Consumption
– Burst Mode Read: 90 mA @ 75 MHz max
– Program/Erase: 50 mA max
Publication Number
S29CD-G_00
Revision
B
Amendment
0
Issue Date
November 14, 2005
This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qual-
ification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document
may be revised by subsequent versions or modifications due to changes in technical specifications.
Data
Sheet
(Pre limin ar y)
General Description
The S29CD-G Flash Family is a burst mode, Dual Boot, Simultaneous Read/Write family of Flash Memory
with VersatileI/O™ manufactured on 170 nm Process Technology.
The S29CD032G is a 32 Megabit, 2.6 Volt-only (2.50 V - 2.75 V) single power supply burst mode flash
memory device that can be configured for 1,048,576 double words.
The S29CD016G is a 16 Megabit, 2.6 Volt-only (2.50 V - 2.75 V) single power supply burst mode flash
memory device that can be configured for 524,288 double words.
To eliminate bus contention, each device has separate chip enable (CE#), write enable (WE#) and output
enable (OE#) controls. Additional control inputs are required for synchronous burst operations: Load Burst
Address Valid (ADV#), and Clock (CLK).
Each device requires only a single 2.6 Volt-only (2.50 V – 2.75 V) for both read and write functions. A 12.0-
volt V
PP
is not required for program or erase operations, although an acceleration pin is available if faster
programming performance is required.
The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. The
software command set is compatible with the command sets of the 5 V Am29F or MBM29F and 3 V Am29LV
or MBM29LV Flash families. Commands are written to the command register using standard microprocessor
write timing. Register contents serve as inputs to an internal state-machine that controls the erase and
programming circuitry. Write cycles also internally latch addresses and data needed for the programming and
erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.
The
Unlock Bypass
mode facilitates faster programming times by requiring only two write cycles to program
data instead of four.
The
Simultaneous Read/Write architecture
provides simultaneous operation by dividing the memory space
into two banks. The device can begin programming or erasing in one bank, and then simultaneously read
from the other bank, with zero latency. This releases the system from waiting for the completion of program or
erase operations. See
Simultaneous Read/Write Operations Overview
on page 23.
The device provides a 256-byte
Secured Silicon Sector
that contains Electronic Marking Information for
easy device traceability.
In addition, the device features several levels of sector protection, which can disable both the program and
erase operations in certain sectors or sector groups:
Persistent Sector Protection
is a command sector
protection method that replaces the old 12 V controlled protection method;
Password Sector Protection
is a
highly sophisticated protection method that requires a password before changes to certain sectors or sector
groups are permitted;
WP# Hardware Protection
prevents program or erase in the two outermost 8 Kbytes
sectors of the larger bank.
The device defaults to the Persistent Sector Protection mode. The customer must then choose if the
Standard or Password Protection method is most desirable. The WP# Hardware Protection feature is always
available, independent of the other protection method chosen.
The
VersatileI/O™ (V
CCQ
)
feature allows the output voltage generated on the device to be determined based
on the V
IO
level. This feature allows this device to operate in the 1.8 V I/O environment, driving and receiving
signals to and from other 1.8 V devices on the same bus.
The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin,
by reading the DQ7 (Data# Polling), or DQ6 (toggle)
status bits.
After a program or erase cycle is completed,
the device is ready to read array data or accept another command.
The
sector erase architecture
allows memory sectors to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully erased when shipped from the factory.
Hardware data protection
measures include a low V
CC
detector that automatically inhibits write operations
during power transitions. The
password and software sector protection
feature disables both program and
erase operations in any combination of sectors of memory. This can be achieved in-system at V
CC
level.
The
Program/Erase Suspend/Erase Resume
feature enables the user to put erase on hold for any period of
time to read data from, or program data to, any sector that is not selected for erasure. True background erase
can thus be achieved.
The
hardware RESET# pin
terminates any operation in progress and resets the internal state machine to
reading array data.
2
S29CD-G Flash Family
S29CD-G_00_B0 November 14, 2005
Da ta
Shee t
(Prelimi nar y)
The device offers two power-saving features. When addresses are stable for a specified amount of time, the
device enters the
automatic sleep mode.
The system can also place the device into the
standby mode.
Power consumption is greatly reduced in both these modes.
AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest
levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector
simultaneously via Fowler-Nordheim tunnelling. The data is programmed using hot electron injection.
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