D ts e t
aa h e
R c e t r lc r nc
o h se Ee to is
Ma u a t r dCo o e t
n fc u e
mp n n s
R c e tr b a d d c mp n ns ae
o h se rn e
o oet r
ma ua trd u ig ete dewaes
n fcue sn i r i/ fr
h
p rh s d f m te oiia s p l r
uc a e r
o h r n l u pi s
g
e
o R c e tr waes rce td f m
r o h se
fr e rae r
o
te oiia I. Al rce t n ae
h
r nl P
g
l e rai s r
o
d n wi tea p o a o teOC
o e t h p rv l f h
h
M.
P r aetse u igoiia fcoy
at r e td sn r n la tr
s
g
ts p o rmso R c e tr e eo e
e t rga
r o h se d v lp d
ts s lt n t g aa te p o u t
e t oui s o u rne
o
rd c
me t o e c e teOC d t s e t
es r x e d h
M aa h e.
Qu l yOv riw
ai
t
e ve
• IO- 0 1
S 90
•A 92 cr ct n
S 1 0 et ai
i
o
• Qu l e Ma ua trr Ls (
ai d
n fcues it QML MI- R -
) LP F
385
53
•C a sQ Mitr
ls
lay
i
•C a sVS a eL v l
ls
p c ee
• Qu l e S p l r Ls o D sr uos( L )
ai d u pi s it f it b tr QS D
e
i
•R c e trsacic l u pir oD A a d
o h se i
r ia s p l t L n
t
e
me t aln u t a dD A sa d r s
es lid sr n L tn ad .
y
R c e tr lcrnc , L i c mmi e t
o h se Ee t is L C s o
o
tdo
t
s p ligp o u t ta s t f c so r x e t-
u pyn rd cs h t ai y u tme e p ca
s
t n fr u lya daee u loto eoiial
i s o q ai n r q a t h s r n l
o
t
g
y
s p l db id sr ma ua trr.
u pi
e yn ut
y n fcues
T eoiia ma ua trr d ts e t c o a yn ti d c me t e e t tep r r n e
h r n l n fcue’ aa h e a c mp n ig hs o u n r cs h ef ma c
g
s
o
a ds e ic t n o teR c e tr n fcue v rino ti d vc . o h se Ee t n
n p c ai s f h o h se ma ua trd eso f hs e ie R c e tr lcr -
o
o
isg aa te tep r r n eo i s mio d co p o u t t teoiia OE s e ic -
c u rne s h ef ma c ft e c n u tr rd cs o h r n l M p c a
o
s
g
t n .T pc lv le aefr eee c p r o e o l. eti mii m o ma i m rt g
i s ‘y ia’ au s r o rfrn e up s s ny C r n nmu
o
a
r xmu ai s
n
ma b b s do p o u t h rceiain d sg , i lt n o s mpetsig
y e a e n rd c c aa tr t , e in smuai , r a l e t .
z o
o
n
© 2 1 R cetr l t n s LC Al i t R sre 0 1 2 1
0 3 ohs E cr i , L . lRg s eevd 7 1 0 3
e e oc
h
T l r m r, l s v iw wrcl . m
o e n oe p ae it w . e c o
a
e
s
o ec
ON Semiconductort
Low Power, High Slew Rate,
Wide Bandwidth, JFET Input
Operational Amplifiers
Quality bipolar fabrication with innovative design concepts are employed
for the MC33181/2/4, MC34181/2/4 series of monolithic operational
amplifiers. This JFET input series of operational amplifiers operates at
210
µA
per amplifier and offers 4.0 MHz of gain bandwidth product and
10 V/µs slew rate. Precision matching and an innovative trim technique of
the single and dual versions provide low input offset voltages. With a JFET
input stage, this series exhibits high input resistance, low input offset voltage
and high gain. The all NPN output stage, characterized by no deadband
crossover distortion and large output voltage swing, provides high
capacitance drive capability, excellent phase and gain margins, low open
loop high frequency output impedance and symmetrical source/sink AC
frequency response.
The MC33181/2/4, MC34181/2/4 series of devices are specified over the
commercial or industrial/vehicular temperature ranges. The complete series
of single, dual and quad operational amplifiers are available in the plastic
DIP as well as the SOIC surface mount packages.
•
Low Supply Current: 210
µA
(Per Amplifier)
8
MC34181,2,4
MC33181,2,4
8
1
1
P SUFFIX
PLASTIC PACKAGE
CASE 626
D SUFFIX
PLASTIC PACKAGE
CASE 751
(SO–8)
PIN CONNECTIONS
Offset Null
Inputs
V
EE
1
2
3
4
-
+
8
7
6
5
NC
V
CC
Output
Offset Null
(Single, Top View)
Output 1
Inputs 1
V
EE
1
2
3
4
-
+
1
2
-
+
8
7
6
5
V
CC
Output 2
Inputs 2
•
•
•
•
•
•
•
•
•
•
•
Wide Supply Operating Range:
±1.5
V to
±18
V
Wide Bandwidth: 4.0 MHz
High Slew Rate: 10 V/µs
Low Input Offset Voltage: 2.0 mV
Large Output Voltage Swing: –14 V to +14 V (with
±15
V Supplies)
Large Capacitance Drive Capability: 0 pF to 500 pF
Low Total Harmonic Distortion: 0.04%
Excellent Phase Margin: 67°
Excellent Gain Margin: 6.7 dB
Output Short Circuit Protection
Offered in New TSSOP Package Including the Standard SOIC and
DIP Packages
ORDERING INFORMATION
Op Amp
Function
Single
Device
MC34181P
MC34181D
MC33181P
MC33181D
Dual
MC34182P
MC34182D
MC33182P
MC33182D
Quad
MC34184P
MC34184D
MC34184DTB
MC33184P
MC33184D
MC33184DTB
Operating
Temperature Range
T
A
= 0° to +70°C
T
A
= –40° to +85°C
T
A
= 0° to +70°C
T
A
= –40° to +85°C
Package
Plastic DIP
SO–8
Plastic DIP
SO–8
Plastic DIP
SO–8
Plastic DIP
SO–8
Plastic DIP
SO–14
TSSOP–14
Plastic DIP
SO–14
TSSOP–14
14
1
(Dual, Top View)
14
1
P SUFFIX
PLASTIC PACKAGE
CASE 646
14
1
D SUFFIX
PLASTIC PACKAGE
CASE 751A
(SO–14)
DTB SUFFIX
PLASTIC PACKAGE
CASE 948G
(TSSOP–14)
PIN CONNECTIONS
Output 1
Inputs 1
V
CC
Inputs 2
Output 2
1
2
3
4
5
6
7
+
-
+
-
-
+
-
-
+
14
13
12
11
10
9
8
Output 4
Inputs 4
V
EE
Inputs 3
Output 3
1
4
2
3
T
A
= 0° to +70°C
T
A
= –40° to +85°C
(Quad, Top View)
©
Semiconductor Components Industries, LLC, 2002
1
March, 2002 – Rev. 2
Publication Order Number:
MC34181/D
MC34181,2,4 MC33181,2,4
MAXIMUM RATINGS
Rating
Supply Voltage (from V
CC
to V
EE
)
Input Differential Voltage Range
Input Voltage Range
Output Short Circuit Duration (Note 2)
Operating Junction Temperature
Storage Temperature Range
Symbol
V
S
V
IDR
V
IR
t
SC
T
J
T
stg
Value
+36
Note 1
Note 1
Indefinite
+150
–60 to +150
Unit
V
V
V
sec
°C
°C
NOTES:
1. Either or both input voltages should not exceed the magnitude of V
CC
or V
EE
.
2. Power dissipation must be considered to ensure maximum junction temperature (T
J
) is not
exceeded (see Figure 1).
Representative Schematic Diagram
(Each Amplifier)
V
CC
Q
8
Q
9
Pos
C
1
Q
7
D
1
R
6
Q
4
Q
3
R
2
I
3
R
3
V
EE
1
5
R
4
R
5
Q
5
I
4
Q
6
D
2
C
2
R
7
V
O
D
3
Internal
Bias
Network
Neg
J
1
+
Q
1
Q
2
R
1
J
2
Null Offsets
MC3X181 (Single) Only
-
+
1
25 kΩ
MC3X181 Input Offset
Voltage Null CIrcuit
5
V
EE
http://onsemi.com
2
MC34181,2,4 MC33181,2,4
DC ELECTRICAL CHARACTERISTICS
(V
CC
= +15 V, V
EE
= –15 V, T
A
= 25°C, unless otherwise noted.)
Characteristics
Input Offset Voltage (R
S
= 50
Ω,
V
O
= 0 V)
Single
T
A
= +25°C
T
A
= 0° to +70°C (MC34181)
T
A
= –40° to +85°C (MC33181)
Dual
T
A
= +25°C
T
A
= 0° to +70°C (MC34182)
T
A
= –40° to +85°C (MC33182)
Quad
T
A
= +25°C
T
A
= 0° to +70°C (MC34184)
T
A
= –40° to +85°C (MC33184)
Average Temperature Coefficient of V
IO
(R
S
= 50
Ω,
V
O
= 0V)
Input Offset Current (V
CM
= 0 V, V
O
= 0V)
T
A
= +25°C
T
A
= 0° to +70°C
T
A
= –40° to +85°C
Input Bias Current (V
CM
= 0 V, V
O
= 0V)
T
A
= +25°C
T
A
= 0° to +70°C
T
A
= –40° to +85°C
Input Common Mode Voltage Range
Large Signal Voltage Gain (R
L
= 10 kΩ, V
O
=
±10
V)
T
A
= +25°C
T
A
= T
low
to T
high
Output Voltage Swing (V
ID
= 1.0 V, R
L
= 10 kΩ)
T
A
= +25°C
Common Mode Rejection (R
S
= 50
Ω,
V
CM
= V
ICR
, V
O
= 0 V)
Power Supply Rejection (R
S
= 50
Ω,
V
CM
= 0 V, V
O
= 0 V)
Output Short Circuit Current (V
ID
= 1.0 V, Output to Ground)
Source
Sink
Power Supply Current (No Load, V
O
= 0 V)
Single
T
A
= +25°C
T
A
= T
low
to T
high
Dual
Symbol
V
IO
Min
Typ
Max
Unit
mV
—
—
—
—
—
—
—
—
—
∆V
IO
/∆T
I
IO
—
—
—
I
IB
—
—
—
V
ICR
A
VOL
25
15
V
O
+
V
O
–
CMR
PSR
I
SC
3.0
8.0
I
D
—
—
—
—
—
—
+13.5
—
70
70
—
0.5
—
—
1.0
—
—
4.0
—
—
10
0.001
—
—
0.003
—
—
2.0
3.0
3.5
3.0
4.0
4.5
10
11
11.5
—
0.05
1.0
2.0
nA
0.1
2.0
4.0
V
V/mV
µV/°C
nA
(V
EE
+4.0 V) to (V
CC
–2.0 V)
60
—
+14
–14
86
84
8.0
11
—
—
—
–13.5
—
—
—
—
V
dB
dB
mA
µA
210
—
420
—
840
—
250
250
500
500
1000
1000
T
A
= +25°C
T
A
= T
low
to T
high
Quad
T
A
= +25°C
T
A
= T
low
to T
high
http://onsemi.com
3
MC34181,2,4 MC33181,2,4
AC ELECTRICAL CHARACTERISTICS
(V
CC
= +15 V, V
EE
= –15 V, T
A
= 25°C, unless otherwise noted.)
Characteristics
Slew Rate (V
in
= –10 V to +10 V, R
L
= 10 kΩ, C
L
= 100 pF)
A
V
= +1.0
A
V
= –1.0
Settling Time (A
V
= –1.0, R
L
= 10 kΩ, V
O
= 0 V to +10 V Step)
To Within 0.10%
To Within 0.01%
Gain Bandwidth Product (f = 100 kHz)
Power Bandwidth (A
V
= +1.0, R
L
= 10 kΩ, V
O
= 20 V
pp
, THD = 5.0%)
Phase Margin (–10 V < V
O
< +10 V)
R
L
= 10 kΩ
R
L
= 10 kΩ, C
L
= 100 pF
Gain Margin (–10 V < V
O
< +10 V)
R
L
= 10 kΩ
R
L
= 10 kΩ, C
L
= 100 pF
Equivalent Input Noise Voltage
R
S
= 100
Ω,
f = 1.0 kHz
Equivalent Input Noise Current
f = 1.0 kHz
Differential Input Capacitance
Differential Input Resistance
Total Harmonic Distortion
A
V
= 10, R
L
= 10 kΩ, 2.0 V
pp
< V
O
< 20 V
pp
, f = 1.0 kHz
Channel Separation (R
L
= 10 kΩ, –10 V < V
O
< +10 V, 0 Hz < f < 10 kHz)
Open Loop Output Impedance
(f = 1.0 MHz)
Symbol
SR
7.0
—
t
s
—
—
GBW
BW
p
f
m
—
—
A
m
—
—
e
n
i
n
C
i
R
i
THD
—
|Z
o
|
—
—
—
—
—
—
—
6.7
3.4
38
0.01
3.0
10
12
0.04
120
200
—
—
—
—
—
—
—
—
—
nV/
√
Hz
pA/
√
Hz
pF
W
%
dB
Ω
67
34
—
—
dB
3.0
—
1.1
1.5
4.0
120
—
—
—
—
MHz
kHz
Degrees
10
10
—
—
µs
Min
Typ
Max
Unit
V/µs
Figure 1. Maximum Power Dissipation versus
Temperature for Package Variations
P D , MAXIMUM POWER DISSIPATION (mW)
V ICR, INPUT COMMON MODE VOLTAGE
RANGE (V)
2400
2000
8/14 Pin
Plastic
TSSOP-14
SO-14
SO-8
0
-1.0
-2.0
3.0
2.0
1.0
Figure 2. Input Common Mode Voltage Range
versus Temperature
V
CC
= +3.0 V to +15 V
V
EE
= -3.0 V to -15 V
∆V
IO
= 5.0 mV
V
CC
(V
CM
to V
CC
)
1600
1200
800
400
0
-55 -40 -20
0
20 40 60 80 100 120 140 160
T
A
, AMBIENT TEMPERATURE (°C)
0
-55
V
EE
-25
0
25
50
75
T
A
, AMBIENT TEMPERATURE (°C)
100
125
http://onsemi.com
4
京公网安备 11010802033920号
EEWORLD
