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AS4DDR232M64PBG-5/IT

Description
DDR DRAM, 32MX64, 0.6ns, CMOS, PBGA255, 25 X 32 MM, 1.27 MM PITCH, PLASTIC, BGA-255
Categorystorage    storage   
File Size300KB,28 Pages
ManufacturerMicross
Websitehttps://www.micross.com
Download Datasheet Parametric View All

AS4DDR232M64PBG-5/IT Overview

DDR DRAM, 32MX64, 0.6ns, CMOS, PBGA255, 25 X 32 MM, 1.27 MM PITCH, PLASTIC, BGA-255

AS4DDR232M64PBG-5/IT Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerMicross
Parts packaging codeBGA
package instructionBGA,
Contacts255
Reach Compliance Codeunknown
ECCN codeEAR99
access modeFOUR BANK PAGE BURST
Maximum access time0.6 ns
Other featuresAUTO/SELF REFRESH
JESD-30 codeR-PBGA-B255
JESD-609 codee0
length32 mm
memory density2147483648 bit
Memory IC TypeDDR DRAM
memory width64
Number of functions1
Number of ports1
Number of terminals255
word count33554432 words
character code32000000
Operating modeSYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize32MX64
Package body materialPLASTIC/EPOXY
encapsulated codeBGA
Package shapeRECTANGULAR
Package formGRID ARRAY
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
Maximum seat height2.03 mm
self refreshYES
Maximum supply voltage (Vsup)1.9 V
Minimum supply voltage (Vsup)1.7 V
Nominal supply voltage (Vsup)1.8 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formBALL
Terminal pitch1.27 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperatureNOT SPECIFIED
width25 mm
iPEM
2.1 Gb SDRAM-DDR2
AS4DDR232M64PBG
32Mx64 DDR2 SDRAM
iNTEGRATED Plastic Encapsulated Microcircuit
FEATURES
DDR2 Data rate = 667, 533, 400
Available in Industrial, Enhanced and Military Temp
Package:
255 Plastic Ball Grid Array (PBGA), 25 x 32mm
1.27mm pitch
Differential data strobe (DQS, DQS#) per byte
Internal, pipelined, double data rate architecture
4-bit prefetch architecture
DLL for alignment of DQ and DQS transitions with
clock signal
Four internal banks for concurrent operation
(Per DDR2 SDRAM Die)
Programmable Burst lengths: 4 or 8
Auto Refresh and Self Refresh Modes
On Die Termination (ODT)
Adjustable data – output drive strength
1.8V ±0.1V power supply and I/O (VCC/VCCQ)
Programmable CAS latency: 3, 4, 5, or 6
Posted CAS additive latency: 0, 1, 2, 3 or 4
Write latency = Read latency - 1* tCK
Organized as 32M x 64
Weight: AS4DDR232M64PBG ~ 3.5 grams typical
NOTE: Self Refresh Mode available on Industrial and Enhanced temp. only
BENEFITS
SPACE conscious PBGA defined for easy
SMT manufacturability (50 mil ball pitch)
Reduced part count
47% I/O reduction vs Individual CSP approach
Reduced trace lengths for lower parasitic
capacitance
Suitable for hi-reliability applications
Upgradable to 64M x 64 density
(consult factory for info on
AS4DDR264M64PBG)
Configuration Addressing
Parameter
Configuration
Refresh Count
Row Address
Bank Address
Column Address
32 Meg x 72
8 Meg x 16 x 4 Banks
8K
8K (A0 A12)
4 (BA0 BA1)
1K (A0 A9)
FUNCTIONAL BLOCK DIAGRAM
Ax, BA0-2
ODT
VRef
VCC
VCCQ
VSS
VSSQ
VCCL
VSSDL
CS0\
CS1\
CS2\
CS3\
UDMx, LDMx
UDSQx,UDSQx\
LDSQx, LDSQx\
RASx\,CASx\,WEx\
CKx,CKx\,CKEx
A
DQ0-15 B
DQ16-31 C
DQ32-47
2
2
2
3
3
A
VCCL
VSSDL
2
2
2
3
3
B
VCCL
VSSDL
2
2
2
3
3
C
VCCL
VSSDL
2
2
2
3
3
D
AS4DDR232M64PBG
Rev. 1.4 01/10
Micross Components reserves the right to change products or specifications without notice.
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