FT93C56A-ISR-B datasheet, PDF - EEWORLD Datasheet

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FT93C56A-ISR-B: DescriptionEEPROM, 128X16, Serial, CMOS, PDSO8, ROHS COMPLIANT, SOP-8; Categorystorage storage; File Size234KB，19 Pages; ManufacturerFremont Micro Devices USA; Environmental Compliance

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FT93C56A-ISR-B Overview

EEPROM, 128X16, Serial, CMOS, PDSO8, ROHS COMPLIANT, SOP-8

FT93C56A-ISR-B Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Fremont Micro Devices USA
package instruction	SOP,
Reach Compliance Code	unknown
Spare memory width	8
Maximum clock frequency (fCLK)	0.25 MHz
JESD-30 code	R-PDSO-G8
length	4.9 mm
memory density	2048 bit
Memory IC Type	EEPROM
memory width	16
Number of functions	1
Number of terminals	8
word count	128 words
character code	128
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	128X16
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Parallel/Serial	SERIAL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Maximum seat height	1.75 mm
Serial bus type	3-WIRE
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	1.8 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	3.9 mm
Maximum write cycle time (tWC)	10 ms

FT93C56A-ISR-B Preview

93C46/A, 93C56/A, 93C66/A

3-Wire Serial EEPROM

1K, 2K and 4Kbit (8-bit or 16-bit wide)

FEATURES

Standard Voltage and Low Voltage Operation:

•

FT93C46/56/66:

= 2.5V to 5.5V

•

FT93C46A/56A/66A:

= 1.8V to 5.5V

User Selectable Internal Organization:

•

FT93C46:

FT93C56:

128 x 8 or 64 x 16

256 x 8 or 128 x 16

•

FT93C66: 512 x 8 or 256 x 16

2 MHz Clock Rate (5V) Compatibility.

Industry Standard 3-wire Serial Interface.

Self-Timed ERASE/WRITE Cycles (5ms max including auto-erase).

Automatic ERAL before WRAL.

Sequential READ Function.

High Reliability: Typical 1 Million Erase/Write Cycle Endurance.

100 Years Data Retention.

Industrial Temperature Range (-40

C to 85

C).

Standard 8-pin PDIP/SOIC/TSSOP Pb-free Packages.

DESCRIPTION

The FT93C46/56/66 series are 1024/2048/4096 bits of serial Electrical Erasable and Programmable Read Only

Memory, commonly known as EEPROM. They are organized as 64/128/256 words of 16 bits each when the ORG

pin is connected to VCC (or unconnected) and 128/256/512 words of 8 bits (1 byte) each when the ORG pin is tied

to ground. The devices are fabricated with proprietary advanced CMOS process for low power and low voltage

applications. These devices are available in standard 8-lead PDIP, 8-lead JEDEC SOIC and 8-lead TSSOP

packages. Our extended V

range (1.8V to 5.5V) devices enables wide spectrum of applications.

The FT93C46/56/66 is enabled through the Chip Select pin (CS), and accessed via a 3-wire serial interface

consisting of Data Input (DI), Data Output (DO), and Shift Clock (SCL). Upon receiving a READ instruction at DI,

the address is decoded and the data is clocked out serially on the data output pin DO. The WRITE cycle is

completely self-timed and no separate ERASE cycle is required before WRITE. The WRITE cycle is only enabled

when the part is in the ERASE/WRITE ENABLE state. Once a device begins its self-timed program procedure, the

data out pin (DO) can indicate the READY/BUSY status by rising chip select (CS).

DS320E-page1

93C46/A, 93C56/A, 93C66/A

PIN CONFIGURATION

Pin Name

SCL

ORG

VCC

GND

Pin Function

Chip Select

Serial Clock

Serial Data Input

Serial Data Output

Internal Organization

Don’t Connect

Power Supply

Ground

All these packaging types come in Pb-free certified.

SCL

VCC

ORG

GND

SCL

VCC

ORG

GND

8L PDIP

8L SOIC

SCL

VCC

ORG

GND

VCC

SCL

ORG

GND

8L TSSOP

8L SOIC

Rotated (R)

93C46 only

ABSOLUTE MAXIMUM RATINGS

Industrial operating temperature:

Storage temperature:

Input voltage on any pin relative to ground:

Maximum voltage:

-40

C to 85

-50

C to 125

-0.3V to V

+ 0.3V

* Stresses exceed those listed under “Absolute Maximum Rating” may cause permanent damage to the device.

Functional operation of the device at conditions beyond those listed in the specification is not guaranteed.

Prolonged exposure to extreme conditions may affect device reliability or functionality.

DS3020D-page2

93C46/A, 93C56/A, 93C66/A

PIN DESCRIPTIONS

(A) SERIAL CLOCK (SCL)

The rising edge of this SCL input is to latch data into the EEPROM device while the rising edge of this clock is

to clock data out of the EEPROM device.

(B) CHIP SELECT (CS)

This is the chip select input signal for the serial EEPROM device. .

This is data input signal for the serial device.

(D) SERIAL DATA OUTPUT (DO)

This is data output signal for the serial device.

(E) INTERNAL ORGANIZATION (ORG)

This is internal organization input signal for the serial EEPROM device. When the ORG pin is connected to

VCC or unconnected the EEPROM is organized as 64/128/256 word of 16 bits each and when ORG pin is

connected to ground the EEPROM is organized as 128/256/512 byte of 8 bits each. Typically, these signals are

hardwired to either V

or V

. If left unconnected, they are internally recognized as V

DS3020D-page3

93C46/A, 93C56/A, 93C66/A

MEMORY ORGANIZATION

The FT93C46/56/66 memory is organized either as bytes (x8) or as words (x16). If Internal Organization (ORG) is

unconnected (or connected to VCC) the words (x16) organization is selected; When Internal Organization is

connected to ground the bytes (x8) organization is selected.

INSTRUCTION SET for the FT93C46

Instruction

READ

EWEN

EWDS

ERASE

WRITE

ERAL

WRAL

Code

Address

- A

11xxxxx

00xxxxx

- A

10xxxxx

01xxxxx

11xxxx

00xxxx

- A

10xxxx

01xxxx

- D

Data

Reads data stored in memory, at

specified address.

Write enable must precede all

programming modes.

Disables all programming

instructions.

Erase memory location A

- A

Writes memory location A

- A

Erases all memory locations.

Writes all memory locations.

Comments

INSTRUCTION SET for the FT93C56 and FT93C66

Instruction

READ

EWEN

EWDS

ERASE

WRITE

ERAL

WRAL

(A) START BIT (SB)

Each instruction is preceded by a rising edge on Chip Select (CS) with Serial Clock (SCL) being held Low.

(B) OPERATION CODE (OP-CODE)

Two op-code bits, read on Serial Data Input (DI) during the rising edge of Serial Clock (SCL).

The address bits of the byte or word that is to be accessed. For the FT93C46, the address is made up of 6 bits

for the x16 organization or 7 bits for x8 organization. For the FT93C56, the address is made up of 7 bits for the

x16 organization or 8 bits for x8 organization. For the FT93C66, the address is made up of 8 bits for the x16

organization or 9 bits for x8 organization.

(D) DATA

The data bits of the byte or word that is to be accessed. For the FT93C46/56/66, the data is made up of 16 bits

(word) for the x16 organization or 8 bits (byte) for x8 organization.

Code

Address

- A

11xxxxxxx

00xxxxxxx

- A

10xxxxxxx

01xxxxxxx

- A

11xxxxxx

00xxxxxx

- A

10xxxxxx

01xxxxxx

- D

Data

Reads data stored in memory, at

specified address.

Write enable must precede all

programming modes.

Disables all programming

instructions.

Erase memory location A

- A

Writes memory location A

- A

Erases all memory locations.

Writes all memory locations.

Comments

DS3020D-page4

93C46/A, 93C56/A, 93C66/A

INSTRUCTION SETS DESCRIPTION

(A) READ

The Read (READ) instruction contains the Address code for the memory location to be read. After the

instruction and address are decoded, data from the selected memory location is available at the serial output pin

DO. Output data changes are synchronized with the rising edges of serial clock SK. It should be noted that when

a dummy bit (logic “0”) precedes the 8- or 16-bit data output string.

(B) ERASE/WRITE ENABLE

To assure data integrity, the part automatically goes into the Erase/Write Disable (EWDS) state when power is

first applied. An Erase/Write Enable (EWEN) instruction must be executed first before any programming

instructions can be carried out. Please note that once in the Erase/Write Enable state, programming remains

enabled until an Erase/Write Disable (EWDS) instruction is executed or V

power is removed from the part.

To protect against accidental data disturb, the Erase/Write Disable (EWDS) instruction disables all

programming modes and should be executed after all programming operations. The operation of the READ

instruction is independent of both the EWEN and EWDS instructions and can be executed at any time.

(D) ERASE

The Erase (ERASE) instruction programs all bits in the specified memory location to the logical “1” state. The

self-timed erase cycle starts once the ERASE instruction and address are decoded. The DO pin outputs the

READY/BUSY status of the part if CS is brought high after being kept low for a minimum of 250 ns (t

). A

logic “1” at pin DO indicates that the selected memory location has been erased, and the part is ready for

another instruction.

(E) WRITE

The Write (WRITE) instruction contains the 8 or 16 bits of data to be written into the specified memory location.

The self-timed programming cycle, t

, starts after the last bit of data is received at serial data input pin DI. The

DO pin outputs the READY/BUSY status of the part if CS is brought high after being kept low for a minimum

of 250 ns (t

). A logic “0” at DO indicates that programming is still in progress. A logic “1” indicates that the

memory location at the specified address has been written with the data pattern contained in the instruction and

the part is ready for further instructions. A READY/BUSY status cannot be obtained if the CS is brought high

after the end of the self-timed programming cycle, t

(F) ERASE ALL

The Erase All (ERAL) instruction programs every bit in the memory array to the logic “1” state and is primarily

used for testing purposes. The DO pin outputs the READY/BUSY status of the part if CS is brought high after

being kept low for a minimum of 250 ns (t

). The ERAL instruction is valid only at V

= 5.0V ± 10%.

(G) WRITE ALL

The Write All (WRAL) instruction programs all memory locations with the data patterns specified in the

instruction. The DO pin outputs the READY/BUSY status of the part if CS is brought high after being kept low

for a minimum of 250 ns (t

). The WRAL instruction is valid only at V

= 5.0V ± 10%.

DS3020D-page5

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