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TCM29C13, TCM29C14, TCM29C16, TCM29C17,
TCM129C13, TCM129C14, TCM129C16, TCM129C17
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS011H – APRIL 1986 – REVISED JULY 1996
D
D
D
D
D
D
D
D
Replaces Use of TCM2910A in Tandem With
TCM2912C
Reliable Silicon-Gate CMOS Technology
Low Power Consumption:
Operating Mode . . . 80 mW Typical
Power-Down Mode . . . 5 mW Typical
Excellent Power-Supply Rejection Ratio
Over Frequency Range of 0 Hz to 50 kHz
No External Components Needed for
Sample, Hold, and Autozero Functions
Precision Internal Voltage References
Direct Replacement for Intel 2913, 2914,
2916, and 2917
Recommended for Direct Voice
Applications
FEATURES TABLE
FEATURE
Number of Pins:
24
20
16
µ-Law/A-Law
Coding:
µ-Law
A-Law
Gain Timing Rates:
Variable Mode
64 kHz to 2.048 MHz
Fixed Mode
1.536 MHz
1.544 MHz
2.048 MHz
Loopback Test Capability
8th-Bit Signaling
29C13 29C14 29C16 29C17
129C13 129C14 129C16 129C17
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
description
The TCM29C13, TCM29C14, TCM29C16,
TCM29C17, TCM129C13, TCM129C14, TCM129C16, and TCM129C17 are single-chip PCM codecs
(pulse-code-modulated encoders and decoders) and PCM line filters. They provide all the functions required
to interface a full-duplex (4-wire) voice telephone circuit with a TDM (time-division-multiplexed) system, and are
intended to replace the TCM2910A in tandem with the TCM2912C. Primary applications include:
•
•
•
•
•
Line interface for digital transmission and switching of T1 carrier, PABX, and central office telephone
systems
Subscriber line concentrators
Digital-encryption systems
Digital voice-band data-storage systems
Digital signal processing
TCM29C14, TCM129C14
DW PACKAGE
(TOP VIEW)
VBB
PWRO +
PWRO –
GSR
PDN
CLKSEL
ANLG LOOP
SIGR
DCLKR
PCM IN
FSR/TSRE
DGTL GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
GSX
ANLG IN –
ANLG IN +
ANLG GND
NC
SIGX/ASEL
TSX/DCLKX
PCM OUT
FSX/TSXE
CLKX
CLKR
TCM29C16, TCM29C17,
TCM129C16, TLC129C17
DW OR N PACKAGE
(TOP VIEW)
VBB
PWRO +
PWRO –
PDN
DCLKR
PCM IN
FSR/TSRE
DGTL GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC
GSX
ANLG IN –
ANLG GND
TSX/DCLKX
PCM OUT
FSX/TSXE
CLKR/CLKX
TCM29C13, TCM129C13
DW OR N PACKAGE
(TOP VIEW)
VBB
PWRO +
PWRO –
GSR
PDN
CLKSEL
DCLKR
PCM IN
FSR/TSRE
DGTL GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VCC
GSX
ANLG IN –
ANLG IN +
ANLG GND
SIGX/ASEL
TSX/DCLKX
PCM OUT
FSX/TSXE
CLKR/CLKX
NC – No internal connection
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
©
1996, Texas Instruments Incorporated
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
1
TCM29C13, TCM29C14, TCM29C16, TCM29C17,
TCM129C13, TCM129C14, TCM129C16, TCM129C17
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS011H – APRIL 1986 – REVISED JULY 1996
description (continued)
These devices are designed to perform the transmit encoding (A/D conversion) and receive decoding (D/A
conversion) as well as the transmit and receive filtering functions in a pulse-code-modulated system. They are
intended to be used at the analog termination of a PCM line or trunk.
The TCM129C13, TCM129C14, TCM129C16, TCM129C17, TCM29C13, TCM29C14, TCM29C16, and
TCM29C17 provide the band-pass filtering of the analog signals prior to encoding and after decoding. These
combination devices perform the encoding and decoding of voice and call progress tones as well as the
signaling and supervision information.
The TCM29C13, TCM29C14, TCM29C16, and TCM29C17 are characterized for operation from 0°C to 70°C.
The TCM129C13, TCM129C14, TCM129C16, and TCM129C17 are characterized for operation from – 40°C
to 85°C.
functional block diagram
Transmit Section
Autozero
ANLG IN+
ANLG IN –
GSX
Filter
Sample
and Hold
and DAC
PCM OUT
Comparator
Successive
Approximation
Output
Register
TSX/DCLKX
SIGX/ASEL
Reference
Analog-
to-Digital
Control
Logic
FSX/TSXE
CLKX
Receive Section
Filter
GSR
Gain
Set
Buffer
Sample
and Hold
and DAC
‡
Control
Section
CLKSEL
Control
Logic
PDN
ANLG
LOOP†
PCM IN
DCLKR
SIGR†
PWRO –
Digital-
to-Analog
Control
Logic
Input
Register
PWRO+
Reference
VCC
VBB
DGTL ANLG
GND GND
FSR/TSRE
CLKR†
† TCM29C14 and TCM129C14 only
‡ TCM29C13, TCM29C16, TCM29C17, TCM129C13, TCM129C16, and TCM129C17 only
2
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
TCM29C13, TCM29C14, TCM29C16, TCM29C17,
TCM129C13, TCM129C14, TCM129C16, TCM129C17
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS011H – APRIL 1986 – REVISED JULY 1996
Terminal Functions
TERMINAL NO.
NAME
TCM29C13
TCM129C13
16
17
TCM29C14
TCM129C14
20
21
TCM29C16
TCM29C17
TCM129C16
TCM129C17
13
I
I/O
DESCRIPTION
ANLG GND
ANLG IN +
Analog ground return for all internal voice circuits. Not internally
connected to DGTL GND.
Noninverting analog input to uncommitted transmit operational amplifier.
Internally connected to ANLG GND on TCM129C16, TCM29C16,
TCM129C17, and TCM29C17.
Inverting analog input to uncommitted transmit operational amplifier.
Provides loopback test capability. When this input is high, PWRO + is
internally connected to ANLG IN.
Receive master clock and data clock for the fixed-data-rate mode.
Receive master clock only for variable-data-rate mode. CLKR and CLKX
are internally connected together for TCM129C13, TCM129C16,
TCM129C17, TCM29C13, TCM29C16, and TCM29C17.
Clock-frequency selection. Input must be connected to VBB, VCC, or
ground to reflect the master-clock frequency. When tied to VBB, CLK is
2.048 MHz. When tied to GND, CLK is 1.544 MHz. When tied to VCC,
CLK is 1.536 MHz.
Transmit master clock and data clock for the fixed-data-rate mode.
Transmit master clock only for variable-date-rate mode. CLKR and
CLKX are internally connected for the TCM129C13, TCM129C16,
TCM129C17, TCM29C13, TCM29C16, and TCM29C17.
Fixed or variable-data-rate operation select. When connected to VBB,
the device operates in the fixed-data-rate mode. When DCLKR is not
connected to VBB, the device operates in the variable-data-rate mode,
and DCLKR becomes the receiver data clock. DCLKR then operates at
frequencies from 64 kHz to 2.048 MHz.
Digital ground for all internal logic circuits. Not internally connected to
ANLG GND.
I
Frame synchronization clock input/time-slot enable for receive channel.
In the fixed-data-rate mode, FSR distinguishes between signaling and
nonsignaling frames by a double- or single-length pulse, respectively. In
the variable-data-rate mode, this signal must remain high for the duration
of the time slot. The receive channel enters the standby state when FSR
is TTL low for 300 ms.
Frame-synchronization clock input/time-slot enable for transmit
channel. Operates independently of, but in an analagous manner to,
FSR/TSRE. The transmit channel enters the standby state when FSX is
low for 300 ms.
Input to the gain-setting network on the output power amplifier.
Transmission level can be adjusted over a 12-dB range depending on the
voltage at GSR.
Output terminal of internal uncommitted operational amplifier. Internally,
this is the voice signal input to the transmit filter.
Receive PCM input. PCM data is clocked in on eight consecutive
negative transitions of the receive data clock, which is CLKR in
fixed-data-rate timing and DCLKR in variable-data-rate timing.
Transmit PCM output. PCM data is clocked out on this output on eight
consecutive positive transitions of the transmit data clock, which is CLKX
in fixed-data-rate timing and DCLKX in variable-data-rate timing.
ANLG IN –
ANLG LOOP
CLKR
18
22
7
14
I
I
11
13
9
I
CLKSEL
6
6
I
CLKX
11
14
9
I
DCLKR
7
9
5
I
DGTL GND
FSR/TSRE
10
9
12
11
8
7
FSX/TSXE
12
15
10
I
GSR
4
4
I
GSX
PCM IN
19
8
23
10
15
6
O
I
PCM OUT
13
16
11
O
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
3
TCM29C13, TCM29C14, TCM29C16, TCM29C17,
TCM129C13, TCM129C14, TCM129C16, TCM129C17
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS011H – APRIL 1986 – REVISED JULY 1996
Terminal Functions
TERMINAL NO.
NAME
TCM29C13
TCM129C13
5
2
TCM29C14
TCM129C14
5
2
TCM29C16
TCM29C17
TCM129C16
TCM129C17
4
2
I/O
DESCRIPTION
PDN
PWRO +
I
O
Power-down select. The device is inactive with a TTL low-level input to
this terminal and active with a TTL high-level input to the terminal.
Noninverting output of power amplifier. Can drive transformer hybrids or
high-impedance loads directly in either a differential or a single-ended
configuration
Inverting output of power amplifier. Functionally identical with and
complementary to PWRO +.
Signaling bit output, receive channel. In a fixed-data-rate mode, outputs
the logical state of the 8th bit (LSB) of the PCM word in the most recent
signaling frame.
A-law and
µ-law
operation select. When connected to VBB, A-law is
selected. When connected to VCC or GND,
µ-law
is selected. When not
connected to VBB, a TTL-level input is transmitted as the eighth bit (LBS)
of the PCM word during signaling frames on PCM OUT (TCM29C14 and
TCM129C14 only). SIGX/ASEL is internally connected to provide
µ-law
operational for TCM29C16 and TCM129C16 and A-law operation for
TCM29C17 and TCM129C17.
Transmit channel time-slot strobe (output) or data clock (input) for the
transmit channel. In the fixed-data-rate mode, this terminal is an
open-drain output to be used as an enable signal for a 3-state output
buffer. In the variable-data rate mode, DCLKX becomes the transmit
data clock, which operates at TTL level from 64 kHz to 2.048 MHz.
Most negative supply voltage. Input is – 5 V
±
5%.
Most positive supply voltage. Input is 5 V
±
5%
PWRO –
SIGR
3
3
8
3
O
O
SIGX/ASEL
15
18
I
TSX/DCLKX
14
17
12
I/O
VBB
VCC
1
20
1
24
1
16
4
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