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FT6187-12JC

Description
Standard SRAM, 64KX1, 12ns, CMOS, PDSO24, 0.300 INCH, PLASTIC, SOJ-24
Categorystorage    storage   
File Size472KB,13 Pages
ManufacturerForce Technologies Ltd.
Download Datasheet Parametric View All

FT6187-12JC Overview

Standard SRAM, 64KX1, 12ns, CMOS, PDSO24, 0.300 INCH, PLASTIC, SOJ-24

FT6187-12JC Parametric

Parameter NameAttribute value
MakerForce Technologies Ltd.
Parts packaging codeSOJ
package instructionSOJ,
Contacts24
Reach Compliance Codecompliant
ECCN codeEAR99
Maximum access time12 ns
JESD-30 codeR-PDSO-J24
length15.875 mm
memory density65536 bit
Memory IC TypeSTANDARD SRAM
memory width1
Number of functions1
Number of terminals24
word count65536 words
character code64000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize64KX1
Package body materialPLASTIC/EPOXY
encapsulated codeSOJ
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Parallel/SerialPARALLEL
Maximum seat height3.7592 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationDUAL
width7.5184 mm
FT6187/FT6187L
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
– 10/12/15/20/25/35/45 ns (Commercial)
– 12/15/20/25/35 /45 ns (Industrial)
– 15/20/25/35/45/55/70/85 ns (Military)
Low Power Operation
– 743 mW Active -10
– 660/770 mW Active for -12/15
– 550/660 mW Active for -20/25/35
– 193/220 mW Standby (TTL Input)
– 83/110 mW Standby (CMOS Input) P4C187
– 5.5 mW Standby (CMOS Input)
FT6187L
(Military)
Single 5V±10% Power Supply
Ultra High Speed 64K x 1
Static Cmos Rams
Data Retention with 2.0V Supply (FT6187L
Military)
Separate Data I/O
Three-State Output
TTL Compatible Output
Fully TTL Compatible Inputs
Standard Pinout (JEDEC Approved)
– 22-Pin 300 mil DIP
– 24-Pin 300 mil SOJ
– 22-Pin 290x490 mil LCC
– 28-Pin 350x550 mil LCC
DESCRIPTION
The
FT6187/FT6187L
are 65, 536-bit ultra high speed
static RAMs organised as 64K x 1. The CMOS memories
require no clocks or refreshing and have equal access and
cycle times. The RAMs operate from a single 5V ± 10%
tolerance power supply. Data integrity is maintained for sup-
ply voltages down to 2.0V, typically drawing 10µA.
Access times as fast as 10 nanoseconds are available,
greatly enhancing system speeds. CMOS reduces power
consumption to a low 743mW active, 193/83mW standby
for TTL/CMOS inputs and only 5.5 mW standby for the
FT6187L.
The
FT6187/FT6187L
are available in 22-pin 300 mil DIP,
24-pin 300 mil SOJ, 22-pin and 28-pin LCC packages pro-
viding excellent board level densities.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
DIP (P3, D3, C3)
SOJ (J4)
LCC Pin configurations at end of datasheet.
REV 1.1
1/13
2008
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