AT17N256-10PJ datasheet, PDF - EEWORLD Datasheet

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AT17N256-10PJ: DescriptionConfiguration Memory, 256KX1, Serial, CMOS, PDIP8, 0.300 INCH, PLASTIC, MS-001BA, DIP-8; Categorystorage storage; File Size295KB，18 Pages; ManufacturerAtmel (Microchip); Environmental Compliance

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AT17N256-10PJ Overview

Configuration Memory, 256KX1, Serial, CMOS, PDIP8, 0.300 INCH, PLASTIC, MS-001BA, DIP-8

AT17N256-10PJ Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Atmel (Microchip)
Parts packaging code	DIP
package instruction	DIP,
Contacts	8
Reach Compliance Code	compliant
ECCN code	EAR99
Maximum clock frequency (fCLK)	10 MHz
JESD-30 code	R-PDIP-T8
JESD-609 code	e3
length	9.271 mm
memory density	262144 bit
Memory IC Type	CONFIGURATION MEMORY
memory width	1
Humidity sensitivity level	1
Number of functions	1
Number of terminals	8
word count	262144 words
character code	256000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	256KX1
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
Parallel/Serial	SERIAL
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	5.334 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	NO
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	40
width	7.62 mm

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Features

•

EE Programmable 262,144 x 1-, 524,288 x 1-, 1,048,576 x 1-, 2,097,152 x 1-, and

•

4,194,304 x 1-bit Serial Memories Designed to Store Configuration Programs for Field

Programmable Gate Arrays (FPGAs)

Available as a 3.3V (±10%) Commercial and Industrial Version

Simple Interface to SRAM FPGAs

Pin Compatible with Xilinx

XC17SXXXA and XC17SXXXXL PROMs

Compatible with Xilinx Spartan

-II, Spartan-IIE and Spartan XL FPGAs in Master Serial

Mode

Very Low-power CMOS EEPROM Process

Available in 8-lead PDIP, 8-lead SOIC, 20-lead SOIC and 44-lead TQFP Packages for a

Specific Density

Low-power Standby Mode

High-reliability

– Endurance: Minimum 10 Write Cycles

– Data Retention: 20 Years at 85°C

FPGA

Configuration

Memory

AT17N256

AT17N512

AT17N010

AT17N002

AT17N040

3.3V

System Support

Description

The AT17N series FPGA Configuration EEPROM (Configurators) provide an easy-to-

use, cost-effective configuration memory for Field Programmable Gate Arrays. The

AT17N series device is packaged in the 8-lead PDIP, 8-lead SOIC, 20-lead SOIC and

44-lead TQFP, see Table 1. The AT17N series Configurators uses a simple serial-

access procedure to configure one or more FPGA devices.

The AT17N series configurators can be programmed with industry-standard program-

mers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable and

factory programming.

Table 1.

AT17N Series Packages

Package

8-lead PDIP

8-lead SOIC

20-lead SOIC

44-lead TQFP

AT17N256

Yes

–

AT17N512/

AT17N010

Yes

–

Yes

–

AT17N002

–

Yes

AT17N040

–

Yes

3020C–CNFG–08/07

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