STDGLA-13.500 datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Passive components> oscillator> STDGLA-13.500

STDGLA-13.500: DescriptionCMOS/TTL Output Clock Oscillator, 1.024MHz Min, 65.54MHz Max, 13.5MHz Nom; CategoryPassive components oscillator; File Size159KB，6 Pages; ManufacturerVectron International, Inc.; Websitehttp://www.vectron.com/; Environmental Compliance

Download Datasheet Parametric View All

STDGLA-13.500 Overview

CMOS/TTL Output Clock Oscillator, 1.024MHz Min, 65.54MHz Max, 13.5MHz Nom

STDGLA-13.500 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Vectron International, Inc.
package instruction	DIP6,.3
Reach Compliance Code	compliant
Maximum control voltage	3 V
Minimum control voltage	0.3 V
maximum descent time	5 ns
Frequency Adjustment - Mechanical	NO
Frequency offset/pull rate	50 ppm
frequency stability	50%
JESD-609 code	e4
Manufacturer's serial number	S
Installation features	THROUGH HOLE MOUNT
Number of terminals	6
Maximum operating frequency	65.54 MHz
Minimum operating frequency	1.024 MHz
Nominal operating frequency	13.5 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	CMOS/TTL
Output load	5 TTL
Package body material	METAL
Encapsulate equivalent code	DIP6,.3
physical size	8.51mm x 7.87mm x 3.3mm
power supply	3.3 V
Certification status	Not Qualified
longest rise time	5 ns
Maximum slew rate	13 mA
Nominal supply voltage	3.3 V
surface mount	NO
maximum symmetry	45/55 %
Terminal surface	Gold/Nickel (Au/Ni)

Preview

Download Datasheet

View All

S-Type

Voltage Controlled Crystal Oscillator

Features

•

Output Frequencies to 65.536MHz

•

5 or 3.3 Vdc operation

•

Tri-State Output

•

Low jitter < 6pS rms (for freq >12MHz)

•

VCXO with CMOS outputs

•

0/70 or –40/85

°C

temperature range

•

Hermetically sealed ceramic SMD package

The S-Type Voltage Controlled Crystal

Oscillator

Applications

Output

Buffer /

Tri State

•

SONET/SDH

•

xDSL

•

Digital Video

•

Low jitter PLL’s

ESD Diodes

Description

Input

Buffer

Block Diagram

Figure 1

The VI S-Type Voltage Controlled Crystal

Oscillator (VCXO) is a quartz stabilized square

wave generator with a CMOS output and is

tested at CMOS (3.3 and 5V operation) and TTL

(5 V operation) logic levels. Devices are tested

for absolute pull range (APR) and start-up over

the operating temperature range which insures

the performance and reliability.

Vectron International 166 Glover Avenue, Norwalk CT 06856-5160

Tel:1-88-VECTRON-1

e-mail: vectron@vectron.com

S-Type Voltage Controlled Crystal Oscillator

Qualification Conformance

The S-Type has undergone the following Mil-Std qualification.

Table 3. Environmental Compliance

Parameter

Mechanical Shock

Mechanical Vibration

Solderability

Gross and Fine Leak

Resistance to Solvents

Conditions

MIL-STD-883C 2002.3, TEST B

MIL-STD-883C 2007.1, TEST C

MIL-STD-883C 2003.5

MIL-STD-883C 1014.7, 100% Tested

MIL-STD-883C 2016

Handling Precautions

Although ESD protection circuitrry has been designed into the the S-Type, proper precautions should be

taken when handling and mounting. VI employs a human body model and a charged-device model (CDM)

for ESD susceptibility testing and design protection evaluation. ESD thresholds are dependent on the

circuit parameters used to define the model. Although no industry wide standard has been adopted for the

CDM, a standard HBM of resistance=1.5Kohms and capacitance = 100pF is widely used and Therefore

can be used for comparison purposes.

Table 4. ESD Ratings

Model

Human Body Model

Charged Device Model

Minimum

1500 V (Mil-STD-883D, Method 3015, Class 1)

1500 V

Absolute Pull Range (APR) Specification

The frequency deviation of the S-Type VCXO is specified in terms of Absolute Pull Range (APR). APR

provides the user with a guaranteed specification for minimum available frequency deviation over all

operating conditions. Operating conditions include operating temperature range, power supply variation,

differences in output loading and changes due to aging.

An S-Type VCXO with an APR of +/-50 ppm will track a +/-50 ppm reference source over all

operating conditions. The same device will typically demonstrate a Total Pull capability of 150 to

350 ppm.

Absolute Pull Range (APR) is specified by the fourth character of the product code in Table 6.

Please see Vectron’s web site,

www.vectron.com,

for the APR Application Note.

Oscillator Aging

Quartz stabilized oscillators typically exhibit a small shift in output frequency during aging. The major

factors which lead to this shift are changes in the mechanical stress on the crystal and mass-loading of

foreign material on the crystal.

As the oscillator ages, relaxation of the crystal mounting stress or transfer of environmental stress through

the package to the crystal mounting arrangement can lead to frequency variations. VI has minimized these

two effects through the use of a miniature AT-Cut strip resonator crystal which allows a superior mounting

arrangement and results in minimal relaxation and almost negligible environmental stress transfer.

Vectron International

•

166 Glover Avenue, Norwalk, CT 06856

•

Tel: 1-88-VECTRON-1• http://www.vectron.com

Recommended Resources

Do you know the possible reasons why the power adapter cannot be used universally?

Blood pressure sensing circuit diagram of BP01 pressure sensor

Power supply circuit diagram of AST-1401 VGA color display

Low speed jog control circuit

DT860 type 3 1/2 digit automatic range digital multimeter circuit

Computer motherboard circuit diagram 815 3_02

Today I went to the schematic diagram of the 4-layer board in the previous activity. The level conversion chip also has a switching power supply chip. I want to ask the difference: Switching power supply chips also convert a voltage value into another voltage value, such as: 12V->5V 12V->3.3V Level conversion chips also have 3.3V->5V 5V->3.3V What I searched is that level conver...; chen468859 PCB Design

[AN-1169 Application Note] Linear Gain Setting Mode: Detailed Description: Introduction Digital potentiometers are often used to digitally program the gain in amplifiers or to set the output voltage of power regulators, as shown in Figures 1 and 2....; EEWORLD社区 ADI Reference Circuit

Spartan-6 FPGA Embedded Kit Trial (Part 1): When I got this board, I couldn't wait to open it and take a look. I was impressed by the powerful functions of the board, but I didn't know where to start. For a Xilinx novice like me, it is too adva...; chenzhufly FPGA/CPLD

Who has pedometer algorithm resources based on the LSI3DH chip?: Does anyone have pedometer algorithm resources or links based on the LSI3DH chip? I am using ST's LSI3DH for work and urgently need to design a simple pedometer, but I don't know how to get the number...; quake702 Mobile and portable

FPGA Beginner Program: There are programs for buzzer, voting machine, linear block codec, digital tube, and frequency divider. Haha~...; sunnyzhu12 FPGA/CPLD

Where is the TOC stored?: As the title says, where is the TOC stored? I see two statements: 1. It is stored in Nandflash block 1 (right after nboot). 2. It is stored in the OS Image, find "cece" and add an offset. Are the "TOC...; shrlyq Embedded System

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components