512Mb M-die DDR2 SDRAM
Contents
1. Key Feature
2. Package Pinout/Mechnical Dimension & Addressing
2.1 Package Pintout & Mechnical Dimension
2.2 Input/Output Function Description
2.3 Addressing
3. Functional Description
3.1 Simplified State Diagram
3.2 Basic Functionality
3.2.1 Power-Up and Initialization
3.2.2 Programming the Mode Register
3.2.2.1 Mode Register Set(MRS)
3.2.2.2 Extended Mode Register Set(EMRS)
3.2.2.3 OCD Impedance Adjustment-Protocol
3.2.2.4 ODT (On-die termination)
3.2.3 Bank Activate Command
3.2.4 Read and write Access Modes
3.2.4.1 Posted CAS
3.2.4.2 4 bit or 8 bit Burst Mode operation
3.2.4.3 Burst Read opeartion
3.2.4.4 Burst write operation
3.2.4.5 Write data mask
3.2.5 Precharge operation
3.2.6 Auto-Precharge operation
3.2.7 Refresh
3.2.8 Self Refresh
3.2.9 Power Down mode
Preliminary
4. Command Truth Table
5. Absolute Maximum Rating
6. AC & DC Operating Conditions & Specifications
Rev. 0.92 (Jun. 2003)
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512Mb M-die DDR2 SDRAM
Revision History
Version 0.0 (Feb, 2002)
Preliminary
- Initial Release
Version 0.1 (Mar, 2002)
- Corrected the typo
- Add FBGA package dimension
- Delete SS800 AC parameter table
- Changed the CAS Latency & Additive Latency
CAS Latency : removed CL=2(Optional) and changed CL=5(Optional) to CL=5 & Added CL=6(Optional)
Additive Latency : Changed AL=4(Optional) to AL=4 & Added AL=5
- Delete tHZ min
- tIH/tIS for DDR2-533 : min 500ps(from TBD)
- tRRD : differentiate 1KB & 2KB page size as 7.5ns & 10ns each
- tWTR : Changed to analog value(400Mbps : 10ns, 533Mbps + : 7.5ns)
Version 0.11 (April, 2002)
- Corrected typo
- Changed Additive Latency definition as below
Old : AL=0(Default), 1,2,3,4 and 5
New : AL=0,1,2,3 and 4
- Added Comment of Max. Package dimension
Maximum Package Height : 21mm
Maximum Package Center to Center spacing : 12.8mm
Version 0.12 (May 2002)
- BL = 8 and corresponding modification
- Added reads interupted by a read and writes interrupted by a write section
Version 0.13 (September, 2002)
- tRTP concept and example timing diagrams are added
- Power down mode session is updated to describe CKE function more clearly
- Command and CKE truth table formats have been changed. No function change
- Self refresh session is updated. Instead of tXP, tXSNR and tXSRD are used. Improvement from previous
version.
- A12 of EMRS(1), Qff function is added as an optional feature.
Version 0.14 (October, 2002)
- Corrected typos
- Added VDLL(Voltage for DLL) in absolute maximum ratings.
- Removed DDR2-667, ss800 AC parameter table.
Version 0.8 (November, 2002)
- Added a description about OCD default mode.
- tRRD is changed from number of clock to “ns”, 7.5ns for 1KB page, 10ns for 2KB page size products repec-
tively.
- Added speed bin table and corresponding tRCD, tRP and tRC
- Added differential signal spec (definition and basic timing diagram, V
ID
, V
IX
, V
OX
)
- Power up and initialization sequence is more clearly described.
- Added ODT timing at power down mode.
- Added IDD Specification Parameters and Test Conditions.
Rev. 0.92 (Jun. 2003)
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512Mb M-die DDR2 SDRAM
Version 0.9 (January, 2003)
- Added additioinal notes on AC spec table
- Changed nomenclator : from DDR-II to DDR2
Preliminary
Version 0.91 (March 2003)
- Re-worded power-up and initialization sequence
- Added clock frequency change procedure during precharge power down in section 3.2.9 power down mode
- Added CKE Asynchronous Event in section 3.2.9
- Added full strength driver I/V characteristics
- Added overshoot/undershoo specification
- Added AC parameters: tCCD, tRAS(max), tOIT, tDelay
- Changed tWTR spec from 2*tCK to analog value
- Reordered pages and corrected typos
Version 0.92 (Jun. 2003)
- Corrected typo: from 2(optional) to reserved in CAS latency of page18
- Changed package thickness from 0.95 +0.05 to MAX. 1.20.
Rev. 0.92 (Jun. 2003)
Page 4 of 80
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