GS84032GT-166I datasheet, PDF - EEWORLD Datasheet

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GS84032GT-166I: DescriptionCache SRAM, 128KX32, 8.5ns, CMOS, PQFP100, TQFP-100; Categorystorage storage; File Size628KB，31 Pages; ManufacturerGSI Technology; Websitehttp://www.gsitechnology.com/; Environmental Compliance

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GS84032GT-166I Overview

Cache SRAM, 128KX32, 8.5ns, CMOS, PQFP100, TQFP-100

GS84032GT-166I Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	GSI Technology
Parts packaging code	QFP
package instruction	LQFP,
Contacts	100
Reach Compliance Code	unknown
ECCN code	3A991.B.2.B
Maximum access time	8.5 ns
Other features	FLOW-THROUGH OR PIPELINED ARCHITECTURE
JESD-30 code	R-PQFP-G100
JESD-609 code	e3
length	20 mm
memory density	4194304 bit
Memory IC Type	CACHE SRAM
memory width	32
Humidity sensitivity level	3
Number of functions	1
Number of terminals	100
word count	131072 words
character code	128000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	128KX32
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Package shape	RECTANGULAR
Package form	FLATPACK, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	PURE MATTE TIN
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm

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GS84018/32/36T/B-180/166/150/100

TQFP, BGA

Commercial Temp

Industrial Temp

Features

• FT pin for user configurable flow through or pipelined operation.

• Single Cycle Deselect (SCD) Operation.

• 3.3V +10%/-5% Core power supply

• 2.5V or 3.3V I/O supply.

• LBO pin for linear or interleaved burst mode.

• Internal input resistors on mode pins allow floating mode pins.

• Default to Interleaved Pipelined Mode.

• Byte write (BW) and/or global write (GW) operation.

• Common data inputs and data outputs.

• Clock Control, registered, address, data, and control.

• Internal Self-Timed Write cycle.

• Automatic power-down for portable applications.

• JEDEC standard 100-lead TQFP or 119 Bump BGA package.

-180

5.5ns

3.2ns

330mA

8ns

10ns

190mA

-166

6.0ns

3.5ns

310mA

8.5ns

10ns

190mA

-150

6.6ns

3.8ns

275mA

10ns

190mA

-100

10ns

4.5ns

190mA

12ns

15ns

140mA

256K x 18, 128K x 32, 128K x 36

4Mb Sync Burst SRAMs

Flow Through / Pipeline Reads

180Mhz - 100Mhz

3.3V VDD

3.3V & 2.5V I/O

be used. New addresses can be loaded on every cycle with no

degradation of chip performance.

The function of the Data Output register can be controlled by the user

via the FT mode pin/bump (pin 14 in the TQFP and bump 5R in the

BGA, ) . Holding the FT mode pin/bump low places the RAM in Flow

through mode, causing output data to bypass the Data Output

activating the rising edge triggered Data Output Register.

SCD Pipelined Reads

The GS84018/32/36 is an SCD (Single Cycle Deselect) pipelined

synchronous SRAM. DCD (Dual Cycle Deselect) versions are also

available.SCD SRAMs pipeline deselect commands one stage less

than read commands. SCD RAMs begin turning off their outputs

immediately after the deselect command has been captured in the

input registers.

Pipeline

3-1-1-1

Flow Through

2-1-1-1

tCycle

Byte Write and Global Write

Byte write operation is performed by using byte write enable (BW)

input combined with one or more individual byte write signals (Bx). In

addition, Global Write (GW) is available for writing all bytes at one

time, regardless of the Byte Write control inputs.

Sleep Mode

Low power (Sleep mode) is attained through the assertion (High) of

the ZZ signal, or by stopping the clock (CK). Memory data is retained

during Sleep mode.

Functional Description

Applications

The GS84018/32/36 is a 4,718,592 bit (4,194,304 bit for x32 version)

high performance synchronous SRAM with a 2 bit burst address

counter. Although of a type originally developed for Level 2 Cache

applications supporting high performance CPU’s, the device now

finds application in synchronous SRAM applications ranging from

DSP main store to networking chip set support. The GS84018/32/36

is available in a JEDEC standard 100-lead TQFP or 119 Bump BGA

package.

Core and Interface Voltages

The GS84018/32/36 operates on a 3.3V power supply and all inputs/

outputs are 3.3V and 2.5V compatible. Separate output power (V

DDQ

)

pins are used to de-couple output noise from the internal circuit.

Controls

Addresses, data I/O’s, chip enables (E

, E

), address burst control

inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW, GW) are

synchronous and are controlled by a positive edge triggered clock

input (CK). Output enable (G) and power down control (ZZ) are

asynchronous inputs. Burst cycles can be initiated with either ADSP

or ADSC inputs. In Burst mode, subsequent burst addresses are

generated internally and are controlled by ADV. The burst address

counter may be configured to count in either linear or interleave order

with the Linear Burst Order (LBO) input. The Burst function need not

Rev: 2.05 6/2000

1/31

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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