5962D9317709VNC datasheet, PDF

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5962D9317709VNC: DescriptionFIFO, 16KX9, 30ns, Asynchronous, CMOS; Categorystorage storage; File Size2MB，20 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com

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5962D9317709VNC Overview

FIFO, 16KX9, 30ns, Asynchronous, CMOS

5962D9317709VNC Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Microchip
package instruction	0.400 INCH, DFP-28
Reach Compliance Code	compliant
ECCN code	EAR99
Maximum access time	30 ns
Other features	RETRANSMIT
Maximum clock frequency (fCLK)	25 MHz
period time	40 ns
JESD-30 code	R-XDFP-F28
JESD-609 code	e4
memory density	147456 bit
Memory IC Type	OTHER FIFO
memory width	9
Number of functions	1
Number of terminals	28
word count	16384 words
character code	16000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	16KX9
Exportable	NO
Package body material	UNSPECIFIED
encapsulated code	DFP
Encapsulate equivalent code	FL28,.4
Package shape	RECTANGULAR
Package form	FLATPACK
Parallel/Serial	PARALLEL
power supply	5 V
Certification status	Qualified
Filter level	MIL-PRF-38535 Class V
Maximum seat height	3.3 mm
Maximum slew rate	0.11 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal surface	GOLD
Terminal form	FLAT
Terminal pitch	1.27 mm
Terminal location	DUAL
total dose	30k Rad(Si) V
width	10.16 mm

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Features

•

First-in First-out Dual Port Memory

16384 bits x 9 Organization

Fast Flag and Access Times: 15, 30 ns

Wide Temperature Range: -55°C to +125°C

Programmable Half Full Flag

Fully Expandable by Word Width or Depth

Asynchronous Read/Write Operations

Empty, Full and Half Flags in Single Device Mode

Retransmit Capability

Bi-directional Applications

Battery Back-up Operation: 2V Data Retention

TTL Compatible

Single 5V + 10% Power Supply

No Single Event Latch Up Below an LET threshold of 80 MeV/mg/cm

Tested up to a Total Dose of 30 Krads (according to MIL-STD-883 TM1019)

Quality grades: QML Q and V with SMD 5962-93177 and ESSC with Specification

9301/48

Description

The M672061H implements a first-in first-out algorithm, featuring asynchronous

read/write operations. The FULL and EMPTY flags prevent data overflow and under-

flow. The Expansion logic allows unlimited expansion in word size and depth with no

timing penalties. Twin address pointers automatically generate internal read and write

addresses, and no external address information are required for the Atmel FIFOs.

Address pointers are automatically incremented with the write pin and read pin. The 9

bits wide data are used in data communications applications where a parity bit for

error checking is necessary. The Retransmit pin resets the Read pointer to zero with-

out affecting the write pointer. This is very useful for retransmitting data when an error

is detected in the system.

Using an array of eight transistors (8T) memory cell, the M672061H combines an

extremely low standby supply current (typ = 0.1 µA) with a fast access time at 15 ns

over the full temperature range. All versions offer battery backup data retention capa-

bility with a typical power consumption at less than 2 µW.

For military/space applications that demand superior levels of performance and reli-

ability the M672061H is processed according to the methods of the latest revision of

the MIL PRF 38535 (Q and V) or ESCC 9000.

Rad. Tolerant

High Speed

16 Kb x 9

Parallel FIFO with

Programmable

Flag

M672061H

4144K-AERO-04/07

Figure 2.

Reset (write (read) to Programmable Half Full Flag register)

Write Enable (W)

A write cycle is initiated on the falling edge of this input if the Full Flag (FF) is not set.

Data set-up and hold times must be maintained in the rise time of the leading edge of

the Write Enable (W). Data is stored sequentially in the Ram array, regardless of any

current read operation.

Once half the memory is filled, and during the falling edge of the next write operation,

the Half-Full Flag (HF) will be set to low and remain in this state until the difference

between the write and read pointers is less than or equal to half of the total available

memory in the device. The Half-Full Flag (HF) is then reset by the rising edge of the

read operation.

To prevent data overflow, the Full Flag (FF) will go low, inhibiting further write opera-

tions. On completion of a valid read operation, the Full Flag (FF) will go high after TRFF,

allowing a valid write to begin. When the FIFO stack is full, the internal write pointer is

blocked from W, so that external changes to W will have no effect on the full FIFO stack.

Read Enable (R)

A read cycle is initiated on the falling edge of the Read Enable (R) provided that the

Empty Flag (EF) is not set. The data is accessed on a first in/first out basis, not including

any current write operations. After Read Enable (R) goes high, the Data Outputs

(Q0 - Q8) will return to a high impedance state until the next Read operation. When all

the data in the FIFO stack has been read, the Empty Flag (EF) will go low, allowing the

“final” read cycle, but inhibiting further read operations while the data outputs remain in

a high impedance state. Once a valid write operation has been completed, the Empty

Flag (EF) will go high after tWEF and a valid read may then be initiated. When the FIFO

stack is empty, the internal read pointer is blocked from R, so that external changes to R

will have no effect on the empty FIFO stack.

This is a dual-purpose input. In the Depth Expansion Mode, this pin is connected to

ground to indicate that it is the first loaded (see Operating Modes). In the Single Device

Mode, this pin acts as the retransmit input. The Single Device Mode is initiated by con-

necting the Expansion In (XI) to ground.

The M672061H can be set to retransmit data when the Retransmit Enable Control (RT)

input is pulsed low. A retransmit operation will set the internal read point to the first loca-

tion and will not affect the write pointer. Read Enable (R) and Write Enable (W) must be

in the high state during retransmit. The retransmit feature is intended for use when a

number of writes are equal to or less than the depth of the FIFO has occured since the

last RS cycle. The retransmit feature is not compatible with the Depth Expansion Mode

and will affect the Half-Full Flag (HF), in accordance with the relative locations of the

read and write pointers.

First Load/Retransmit

(FL/RT)

M672061H

4144K-AERO-04/07

M672061H

Expansion In (XI)

This input is a dual-purpose pin. Expansion In (XI) is connected to GND to indicate an

operation in the single device mode. Expansion In (XI) is connected to Expansion Out

(XO) of the previous device in the Depth Expansion or Daisy Chain modes.

The Full Flag (FF) will go low, inhibiting further write operations when the write pointer is

one location less than the read pointer, indicating that the device is full. If the read

pointer is not moved after Reset (RS), the Full Flag (FF) will go low after 16384 writes.

The Empty Flag (EF) will go low, inhibiting further read operations when the read pointer

is equal to the write pointer, indicating that the device is empty.

This is a dual-purpose output. In the single device mode, when Expansion In (XI) is con-

nected to ground, this output acts as an indication of a half-full memory.

The M672061H offers a variable offset for the Half Full condition. The offset is loaded

into a register during a reset cycle. When RS is low, the Programmable Half Full Flag

(PHF) can be loaded from the DATA inputs I

- I

by pulsing W low or from the DATA

outputs Q

- Q

by pulsing R low. The offset options are listed in table 1. If PHF is not

loaded during the reset cycle, the default offset will be the half of the total memory of the

device.

The Programmable Half-Full Flag (PHF) will be set to low and will remain set until the

difference between the write and read pointers is less than or equal to the Programma-

ble offset (if the Half Full Flag register has been loaded during the reset cycle) or the half

of the total memory (if the Half Full register has not been loaded during the reset cycle).

After half the memory is filled and on the falling edge of the next write operation, the

Half-Full Flag (HF) will be set to low and will remain set until the difference between the

write and read pointers is less than or equal to half of the total memory of the device.

The Half-Full Flag (HF) is then reset by the rising edge of the read operation.

In the Depth Expansion Mode, Expansion In (XI) is connected to Expansion Out (XO) of

the previous device. This output acts as a signal to the next device in the Daisy Chain by

providing a pulse to the next device when the previous device reaches the last memory

location.

Full Flag (FF)

Empty Flag (EF)

Expansion Out/Half-full

Flag (XO/HF)

Data Output (Q

- Q

)

DATA output for 9-bit wide data. This data is in a high impedance condition whenever

Read (R) is in a high state.

4144K-AERO-04/07

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