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V58C512804SBI-5

Description
DDR DRAM, 64MX8, 0.7ns, CMOS, PDSO66, 0.400 X 0.875 INCH, GREEN, PLASTIC, MS-024FC, TSOP2-66
Categorystorage    storage   
File Size926KB,62 Pages
ManufacturerProMOS Technologies Inc
Download Datasheet Parametric View All

V58C512804SBI-5 Overview

DDR DRAM, 64MX8, 0.7ns, CMOS, PDSO66, 0.400 X 0.875 INCH, GREEN, PLASTIC, MS-024FC, TSOP2-66

V58C512804SBI-5 Parametric

Parameter NameAttribute value
MakerProMOS Technologies Inc
Parts packaging codeTSSOP2
package instruction0.400 X 0.875 INCH, GREEN, PLASTIC, MS-024FC, TSOP2-66
Contacts66
Reach Compliance Codecompliant
ECCN codeEAR99
access modeFOUR BANK PAGE BURST
Maximum access time0.7 ns
Other featuresAUTO/SELF REFRESH
JESD-30 codeR-PDSO-G66
length22.22 mm
memory density536870912 bit
Memory IC TypeDDR DRAM
memory width8
Number of functions1
Number of ports1
Number of terminals66
word count67108864 words
character code64000000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize64MX8
Package body materialPLASTIC/EPOXY
encapsulated codeTSOP2
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE
Certification statusNot Qualified
Maximum seat height1.2 mm
self refreshYES
Maximum supply voltage (Vsup)2.7 V
Minimum supply voltage (Vsup)2.5 V
Nominal supply voltage (Vsup)2.6 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
width10.16 mm
V58C2512(804/404/164)SB
HIGH PERFORMANCE 512 Mbit DDR SDRAM
4 BANKS X 16Mbit X 8 (804)
4 BANKS X 32Mbit X 4 (404)
4 BANKS X 8Mbit X 16 (164)
5
DDR400
Clock Cycle Time (t
CK2.5
)
Clock Cycle Time (t
CK3
)
System Frequency (f
CK max
)
6ns
5ns
200 MHz
6
DDR333
6ns
-
166 MHz
75
DDR266
7.5ns
-
133 MHz
Features
High speed data transfer rates with system frequency
up to 200MHz
Data Mask for Write Control
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2.5, 3
Programmable Wrap Sequence: Sequential
or Interleave
Programmable Burst Length:
2, 4, 8 for Sequential Type
2, 4, 8 for Interleave Type
Automatic and Controlled Precharge Command
Power Down Mode
Auto Refresh and Self Refresh
Refresh Interval: 8192 cycles/64 ms
Available in 60 Ball FBGA AND 66 Pin TSOP II
SSTL-2 Compatible I/Os
Double Data Rate (DDR)
Bidirectional Data Strobe (DQS) for input and output
data, active on both edges
On-Chip DLL aligns DQ and DQs transitions with CK
transitions
Differential clock inputs CK and CK
Power Supply 2.5V ± 0.2V
Power Supply 2.6V ± 0.1V for DDR400
tRAS lockout supported
Concurrent auto precharge option is supported
*Note:
(-5) Supports PC3200 module with 3-3-3 timing
(-6) Supports PC2700 module with 2.5-3-3 timing
(-75) Supports PC2100 module with 2.5-3-3 timing
Description
The V58C2512(804/404/164)SB is a four bank DDR
DRAM organized as 4 banks x 16Mbit x 8 (804), 4 banks x
32Mbit x 4 (404), 4 banks x 8Mbit x 16 (164). The
V58C2512(804/404/164)SB achieves high speed data
transfer rates by employing a chip architecture that
prefetches multiple bits and then synchronizes the output
data to a system clock.
All of the control, address, circuits are synchronized
with the positive edge of an externally supplied clock. I/O
transactions are occurring on both edges of DQS.
Operating the four memory banks in an interleaved
fashion allows random access operation to occur at a
higher rate than is possible with standard DRAMs. A se-
quential and gapless data rate is possible depending on
burst length, CAS latency and speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
0°C to 70°C
V58C2512(804/404/164)SB Rev.1.3 April 2006
Package Outline
JEDEC 66 TSOP II
60 FBGA
CK Cycle Time (ns)
-5
Power
Std.
-6
-75
L
Temperature
Mark
Blank
1

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