S29AL008D Known Good Die
8 Megabit (1 M x 8-Bit/512 K x 16-Bit)
CMOS 3.0 Volt-only, Boot Sector Flash Memory
Datasheet Supplement
Distinctive Characteristics
Single power supply operation
— 2.7 to 3.6 V for read, program, and erase operations
Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically writes
and verifies data at specified addresses
Manufactured on 0.20µm process technology
High performance
— Access times as fast as 70 ns
Ultra low power consumption (typical values
at 5 MHz)
— 200 nA Automatic Sleep mode current
— 200 nA standby mode current
— 7 mA read current
— 15 mA program/erase current
Minimum one million write cycle guarantee
per sector
Compatibility with JEDEC standards
— Pinout and software compatible with single-power
supply Flash
— Superior inadvertent write protection
Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and fifteen
64 Kbyte sectors (byte mode)
— One 8 Kword, two 4 Kword, one 16 Kword, and fifteen
32 Kword sectors (word mode)
— Supports full chip erase
— Sector Protection features:
— A hardware method of locking a sector to prevent
any program or erase operations within that sector
— Sectors can be locked in-system or via programming
equipment
— Temporary Sector Unprotect feature allows code
changes in previously locked sectors
Data# Polling and toggle bits
— Provides a software method of detecting program or
erase operation completion
Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting program or
erase cycle completion
Erase Suspend/Erase Resume
— Suspends an erase operation to read data from, or
program data to, a sector that is not being erased,
then resumes the erase operation
Hardware reset pin (RESET#)
— Hardware method to reset the device to reading array
data
Unlock Bypass Program Command
— Reduces overall programming time when issuing
multiple program command sequences
20-year data retention at 125°
C
— Reliable operation for the life of the system
Top or bottom boot block configurations
available
Tested to datasheet specifications at
temperature
Quality and reliability levels equivalent to
standard packaged components
Publication Number
S29AL008D_KGD
Revision
A
Amendment
3
Issue Date
June 22, 2005
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General Description
The S29AL008D in Known Good Die (KGD) form is an 8 Mbit, 3.0 volt-only Flash
memory. Spansion defines KGD as standard product in die form, tested for func-
tionality and speed. Spansion KGD products have the same reliability and quality
as Spansion products in packaged form.
S29AL008D Features
The S29AL008D is an 8 Mbit, 3.0 volt-only Flash memory organized as 1,048,576
bytes or 524,288 words. The word-wide data (x16) appears on DQ15–DQ0; the
byte-wide (x8) data appears on DQ7–DQ0. To eliminate bus contention, the de-
vice has separate chip enable (CE#), write enable (WE#) and output enable
(OE#) controls.
The device requires only a
single 3.0 volt power supply
for both read and write
functions. Internally generated and regulated voltages are provided for the pro-
gram and erase operations. No V
PP
is required for program or erase operations.
The device can also be programmed in standard EPROM programmers.
The device is entirely command set compatible with the
JEDEC single-power-
supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register contents serve as input to an in-
ternal state-machine that controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed for the programming and
erase operations. Reading data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program command sequence. This
initiates the
Embedded Program
algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies proper cell margin. The
Unlock Bypass
mode facilitates faster programming times by requiring only two
write cycles to program data instead of four.
Device erasure occurs by executing the erase command sequence. This initiates
the
Embedded Erase
algorithm—an internal algorithm that automatically pre-
programs the array (if it is not already programmed) before executing the erase
operation. During erase, the device automatically times the erase pulse widths
and verifies proper cell margin.
The host system can detect whether a program or erase operation is complete by
observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (tog-
gle)
status bits.
After a program or erase cycle is completed, the device is ready
to read array data or accept another command.
The
sector erase architecture
allows memory sectors to be erased and repro-
grammed without affecting the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low V
CC
detector that automat-
ically inhibits write operations during power transitions. The
hardware sector
protection
feature disables both program and erase operations in any combina-
tion of the sectors of memory. This can be achieved in-system or via
programming equipment.
The
Erase Suspend
feature enables the user to put erase on hold for any period
of time to read data from, or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
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S29AL008D Known Good Die
S29AL008D_KGD_A3 June 22, 2005
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The
hardware RESET# pin
terminates any operation in progress and resets the
internal state machine to reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also reset the device, enabling
the system microprocessor to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When addresses are stable for a
specified amount of time, the device enters the
automatic sleep mode.
The
system can also place the device into the
standby mode.
Power consumption is
greatly reduced in both these modes.
Spansion’s Flash technology combines years of Flash memory manufacturing ex-
perience to produce the highest levels of quality, reliability and cost
effectiveness. The device electrically erases all bits within a sector simulta-
neously via Fowler-Nordheim tunneling. The data is programmed using hot
electron injection.
Electrical Specifications
Refer to the S29AL008D data sheet, publication number S29AL008D_00, for full
electrical specifications on the S29AL008D in KGD form.
June 22, 2005 S29AL008D_KGD_A3
S29AL008D Known Good Die
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Product Selector Guide
Family Part Number
Speed Option (V
CC
= 2.7 – 3.6 V)
Max Access Time, t
ACC
(ns)
Max CE# Access, t
CE
(ns)
Max OE# Access, t
OE
(ns)
70
70
70
30
S29AL008D KGD
90
90
90
35
Die Photograph & Pad Locations
20 19 18 17 16 15 14 13 12
11
10 9
8 7 6 5 4 3 2 1
21 22 23
24 25 26 27 28 29 30 31 32
33
34 35 36 37 38 39 40 41
42 43 44
Note:Wirebond
must be 100% within bond pad opening.
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S29AL008D Known Good Die
S29AL008D_KGD_A3 June 22, 2005
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Pad Description
Pads Relative to Die Center
Pad No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Signal
A15
A14
A13
A12
A11
A10
A9
A8
WE#
RESET#
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE#
VSS
OE#
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
VCC
DQ4
DQ12
DQ5
DQ13
DQ6
DQ14
DQ7
DQ15/A-1
VSS
BYTE#
A16
Pad Center (mils)
X
71.110
66.008
60.905
55.803
50.700
45.598
40.496
35.393
25.189
20.086
-19.245
-29.450
-34.553
-39.655
-44.757
-49.860
-54.962
-60.064
-65.167
-70.269
-70.467
-65.365
-60.261
-51.071
-44.610
-39.196
-33.792
-28.378
-22.965
-17.551
-12.146
-6.732
0.649
11.644
17.058
22.462
27.876
33.289
38.703
44.108
49.522
59.721
64.913
70.016
Y
52.729
52.729
52.729
52.729
52.729
52.729
52.729
52.729
52.729
52.729
52.729
52.729
52.729
52.729
52.729
52.729
52.729
52.729
52.729
52.729
-52.707
-52.707
-52.707
-52.707
-52.502
-52.502
-52.502
-52.502
-52.502
-52.502
-52.502
-52.502
-52.502
-52.502
-52.502
-52.502
-52.502
-52.502
-52.502
-52.502
-52.502
-52.707
-52.707
-52.707
X
1.806
1.677
1.547
1.417
1.288
1.158
1.029
0.899
0.640
0.510
-0.489
-0.748
-0.878
-1.007
-1.137
-1.266
-1.396
-1.526
-1.655
-1.785
-1.790
-1.660
-1.531
-1.297
-1.133
-0.996
-0.858
-0.721
-0.583
-0.446
-0.309
-0.171
0.017
0.296
0.433
0.571
0.708
0.846
0.983
1.120
1.258
1.517
1.649
1.778
Pad Center (millimeters)
Y
1.339
1.339
1.339
1.339
1.339
1.339
1.339
1.339
1.339
1.339
1.339
1.339
1.339
1.339
1.339
1.339
1.339
1.339
1.339
1.339
-1.339
-1.339
-1.339
-1.339
-1.334
-1.334
-1.334
-1.334
-1.334
-1.334
-1.334
-1.334
-1.334
-1.334
-1.334
-1.334
-1.334
-1.334
-1.334
-1.334
-1.334
-1.339
-1.339
-1.339
Notes: The coordinates above are relative to the die center and can be used to operate wire bonding equipment.
June 22, 2005 S29AL008D_KGD_A3
S29AL008D Known Good Die
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