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PDM31034SA15SOATR

Description
Standard SRAM, 128KX8, 15ns, CMOS, PDSO32
Categorystorage    storage   
File Size310KB,8 Pages
ManufacturerParadigm Technology Inc
Download Datasheet Parametric View All

PDM31034SA15SOATR Overview

Standard SRAM, 128KX8, 15ns, CMOS, PDSO32

PDM31034SA15SOATR Parametric

Parameter NameAttribute value
MakerParadigm Technology Inc
package instruction,
Reach Compliance Codeunknown
ECCN code3A991.B.2.B
Maximum access time15 ns
JESD-30 codeR-PDSO-J32
memory density1048576 bit
Memory IC TypeSTANDARD SRAM
memory width8
Number of functions1
Number of terminals32
word count131072 words
character code128000
Operating modeASYNCHRONOUS
Maximum operating temperature105 °C
Minimum operating temperature-40 °C
organize128KX8
Package body materialPLASTIC/EPOXY
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Parallel/SerialPARALLEL
Certification statusNot Qualified
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formJ BEND
Terminal locationDUAL
PRELIMINARY
PDM31034
1 Megabit 3.3V Static RAM
128K x 8-Bit
Revolutionary Pinout
Features
n
Description
The PDM31034 is a high-performance CMOS static
RAM organized as 131,072 x 8 bits. Writing is
accomplished when the write enable (WE) and the
chip enable (CE) inputs are both LOW. Reading is
accomplished when WE remains HIGH and CE and
OE are both LOW.
The PDM31034 operates from a single +3.3V power
supply and all the inputs and outputs are fully TTL-
compatible.
The PDM31034 is available in a 32-pin 400 mil plas-
tic SOJ and 300 mil plastic SOJ, and a 32-pin plastic
TSOP (II) package in revolutionary pinout.
1
2
3
4
5
6
High-speed access times
Com’l: 9, 10, 12, 15 and 20 ns
Ind’l.: 12, 15 and 20 ns
Automotive: 15 and 20 ns
Low power operation (typical)
- PDM31034SA
Active: 200 mW
Standby: 15 mW
Single +3.3V (±0.3V) power supply
TTL-compatible inputs and outputs
Packages
Plastic SOJ (400 mil) - SO
Plastic SOJ (300 mil) - TSO
Plastic TSOP (II) - T
n
n
n
n
Functional Block Diagram
A8
Addresses
A0
I/O0
Input
Data
Control
I/O7
Column Address
Buffer
A16
Control
7
Row
Address
Buffer
Row
Decoder
Memory
Array
512 x 256 x 8
(1,048,576)
8
9
10
11
12
1
Column I/O
Column Decoder
CE
WE
OE
A9
Rev. 1.4 - 4/17/98
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