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FDS6815S62Z

Description
Power Field-Effect Transistor, 5.5A I(D), 20V, 0.04ohm, 2-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET, SOIC-8
CategoryDiscrete semiconductor    The transistor   
File Size232KB,6 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
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FDS6815S62Z Overview

Power Field-Effect Transistor, 5.5A I(D), 20V, 0.04ohm, 2-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET, SOIC-8

FDS6815S62Z Parametric

Parameter NameAttribute value
MakerFairchild
Parts packaging codeSOT
package instructionSMALL OUTLINE, R-PDSO-G8
Contacts8
Reach Compliance Codeunknown
ECCN codeEAR99
ConfigurationSEPARATE, 2 ELEMENTS WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage20 V
Maximum drain current (ID)5.5 A
Maximum drain-source on-resistance0.04 Ω
FET technologyMETAL-OXIDE SEMICONDUCTOR
JESD-30 codeR-PDSO-G8
Number of components2
Number of terminals8
Operating modeENHANCEMENT MODE
Package body materialPLASTIC/EPOXY
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Polarity/channel typeP-CHANNEL
Maximum pulsed drain current (IDM)50 A
Certification statusNot Qualified
surface mountYES
Terminal formGULL WING
Terminal locationDUAL
transistor applicationsSWITCHING
Transistor component materialsSILICON

FDS6815S62Z Preview

FDS6815
July 1999
ADVANCE INFORMATION
FDS6815
Dual P-Channel 2.5V Specified PowerTrench
TM
MOSFET
General Description
These P-Channel 2.5V specified MOSFETs are produced
using a rugged gate version of Fairchild's advanced
PowerTrench
TM
process. It has been optimized for
power management applications which require a wide
range of gate drive voltages.
Features
•
•
•
•
•
•
-5.5 A, 20 V. R
DS(ON)
= 0.040
@ V
GS
= –4.5 V
R
DS(ON)
= 0.050
@ V
GS
= –2.5 V
Extended V
GSS
range (
±12V)
for battery applications.
Low gate charge.
Fast switching speed.
High performance trench technology for extremely
low R
DS(ON)
.
High power and current handling capability.
Applications
•
Load switch
•
Battery protection
•
Power management
D2
D1
D1
S2
G2
D2
5
6
7
8
4
3
2
1
SO-8
Symbol
V
DSS
V
GSS
I
D
P
D
G1
S1
Absolute Maximum Ratings
Drain-Source Voltage
Gate-Source Voltage
Drain Current
- Continuous
- Pulsed
T
A
=25 C unless otherwise noted
o
Parameter
Ratings
20
±12
(Note 1a)
Units
V
V
A
W
5.5
50
2.0
Power Dissipation for Dual Operation
Power Dissipation for Single Operation
(Note 1a)
(Note 1b)
(Note 1c)
1.6
1.0
0.9
-55 to +150
°C
T
J
, T
stg
Operating and Storage Junction Temperature Range
Thermal Characteristics
R
θ
JA
R
θ
JC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
78
40
°C/W
°C/W
Package Marking and Ordering Information
Device Marking
FDS6815
1999
Fairchild Semiconductor Corporation
Device
FDS6815
Reel Size
13’’
Tape Width
12mm
Quantity
2500 units
FDS6815 Rev. A
FDS6815
Electrical Characteristics
Symbol
Parameter
T
A
=25
o
C unless otherwise noted
Test Conditions
Min
Typ
Max
Units
OFF CHARACTERISTICS
BV
DSS
I
DSS
I
GSSF
I
GSSR
Drain-Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate-Body Leakage, Forward
Gate-Body Leakage, Reverse
(Note 2)
V
GS
= 0 V, I
D
= -250
µA
V
DS
= -16 V, V
GS
= 0 V
V
GS
= 12 V, V
DS
= 0 V
V
GS
= -12 V, V
DS
= 0 V
-20
1
100
-100
V
µA
nA
nA
ON CHARACTERISTICS
V
GS(TH)
R
DS(ON)
I
D(ON)
Static Drain-Source
On-Resistance
Gate Threshold Voltage
V
DS
= V
GS
, I
D
= -250
µA
V
GS
= -4.5 V, I
D
= -5.5 A
V
GS
= -2.5 V, I
D
= -5 A
V
GS
= -4.5 V, V
DS
= -5.0 V
-0.6
-1.5
0.04
0.05
V
A
On-State Drain Current
25
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
V
SD
Maximum Continuous Drain-Source Diode Forward Current
Drain-Source Diode Forward
Voltage
V
GS
= 0 V, I
S
= -1.3 A
(Note 2)
-1.3
-1.2
A
V
Notes:
1.
R
θJA
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins.
R
θJC
is guaranteed by design while R
θJA
is determined by the user's board design. Thermal rating based on independent single device operation.
a) 78° C/W when
mounted on a 0.5 in
2
pad of 2 oz. copper.
b) 125° C/W when
mounted on a 0.02 in
2
pad of 2 oz. copper.
c) 135° C/W when
mounted on a minimum pad.
Scale 1 : 1 on letter size paper
2.
Pulse Test: Pulse Width
300
µs,
Duty Cycle
2.0%
FDS6815 Rev. A
SO-8 Tape and Reel Data and Package Dimensions
SOIC(8lds) Packaging
Configuration:
Figure 1.0
N
ELECTROSTATIC
SENSITIVE DEVICES
DO NOT SHIP OR STORE NEAR STRONG ELECTROSTATIC
ELECTROMAGNETIC, MAGNETIC OR RADIOACTIVE FIELDS
TNR DATE
PT NUMBER
PEEL STRENGTH MIN ______________ gms
MAX _____________ gms
ESD Label
Antistatic Cover Tape
Conductive Embossed
Carrier Tape
F63TNR
Label
Customized
Label
Pin 1
F852
831N
F852
831N
SOIC-8 Unit Orientation
SOIC (8lds) Packaging Information
Packaging Option
Packaging type
Qty per Reel/Tube/Bag
Reel Size
Box Dimension (mm)
Max qty per Box
Weight per unit (gm)
Weight per Reel (kg)
Note/Comments
Standard
(no flow code)
TNR
2,500
13” Dia
343x64x343
5,000
0.0774
0.6060
L86Z
Rail/Tube
95
-
530x130x83
30,000
0.0774
-
S62Z
Bag
200
-
76x102x127
1,000
0.0774
-
Bulk
D84Z
TNR
500
7” Dia
184x187x47
2,500
0.0774
0.1182
343mm x 342mm x 64mm
Standard Intermediate box
ESD Label
F63TNR Label sample
LOT: CBVK741B019
FSID: FDS9953A
D/C1: D9842
D/C2:
QTY1:
QTY2:
SPEC REV:
CPN:
QTY: 2500
SPEC:
F852
831N
F852
831N
F63TNLabel
F63TNLabel
ESD Label
QARV:
(F63TNR)2
SOIC(8lds) Tape Leader and Trailer
Configuration:
Figure 2.0
Carrier Tape
Cover Tape
Trailer Tape
160mm minimum
Components
Leader Tape
390mm minimum
November 1998, Rev. A
SO-8 Tape and Reel Data and Package Dimensions, continued
SOIC(8lds) Embossed Carrier Tape
Configuration:
Figure 3.0
T
E1
P0
D0
F
K0
Wc
B0
E2
W
Tc
A0
P1
D1
User Direction of Feed
Dimensions are in millimeter
Pkg type
SOIC(8lds)
(12mm)
A0
6.50
+/-0.10
B0
5.30
+/-0.10
W
12.0
+/-0.3
D0
1.55
+/-0.05
D1
1.60
+/-0.10
E1
1.75
+/-0.10
E2
10.25
min
F
5.50
+/-0.05
P1
8.0
+/-0.1
P0
4.0
+/-0.1
K0
2.1
+/-0.10
T
0.450
+/-
0.150
Wc
9.2
+/-0.3
Tc
0.06
+/-0.02
Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481
rotational and lateral movement requirements (see sketches A, B, and C).
20 deg maximum
Typical
component
cavity
center line
0.5mm
maximum
B0
20 deg maximum component rotation
0.5mm
maximum
Sketch A (Side or Front Sectional View)
Component Rotation
A0
Sketch B (Top View)
Typical
component
center line
Sketch C (Top View)
Component lateral movement
SOIC(8lds) Reel Configuration:
Figure 4.0
Component Rotation
W1 Measured at Hub
Dim A
Max
Dim A
max
Dim N
See detail AA
7”
Diameter Option
B Min
Dim C
See detail AA
W3
Dim D
min
13” Diameter Option
W2 max Measured at Hub
DETAIL AA
Dimensions are in inches and millimeters
Tape Size
12mm
Reel
Option
7” Dia
Dim A
7.00
177.8
13.00
330
Dim B
0.059
1.5
0.059
1.5
Dim C
512 +0.020/-0.008
13 +0.5/-0.2
512 +0.020/-0.008
13 +0.5/-0.2
Dim D
0.795
20.2
0.795
20.2
Dim N
5.906
150
7.00
178
Dim W1
0.488 +0.078/-0.000
12.4 +2/0
0.488 +0.078/-0.000
12.4 +2/0
Dim W2
0.724
18.4
0.724
18.4
Dim W3 (LSL-USL)
0.469 – 0.606
11.9 – 15.4
0.469 – 0.606
11.9 – 15.4
12mm
13” Dia
©
1998 Fairchild Semiconductor Corporation
November 1998, Rev. A
SO-8 Tape and Reel Data and Package Dimensions, continued
SOIC-8 (FS PKG Code S1)
1:1
Scale 1:1 on letter size paper
Dimensions shown below are in:
inches [millimeters]
Part Weight per unit (gram): 0.0774
9
September 1998, Rev. A

FDS6815S62Z Related Products

FDS6815S62Z FDS6815D84Z FDS6815L86Z
Description Power Field-Effect Transistor, 5.5A I(D), 20V, 0.04ohm, 2-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET, SOIC-8 Power Field-Effect Transistor, 5.5A I(D), 20V, 0.04ohm, 2-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET, SOIC-8 Power Field-Effect Transistor, 5.5A I(D), 20V, 0.04ohm, 2-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET, SOIC-8
Maker Fairchild Fairchild Fairchild
Parts packaging code SOT SOT SOT
package instruction SMALL OUTLINE, R-PDSO-G8 SMALL OUTLINE, R-PDSO-G8 SMALL OUTLINE, R-PDSO-G8
Contacts 8 8 8
Reach Compliance Code unknown unknown unknown
ECCN code EAR99 EAR99 EAR99
Configuration SEPARATE, 2 ELEMENTS WITH BUILT-IN DIODE SEPARATE, 2 ELEMENTS WITH BUILT-IN DIODE SEPARATE, 2 ELEMENTS WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage 20 V 20 V 20 V
Maximum drain current (ID) 5.5 A 5.5 A 5.5 A
Maximum drain-source on-resistance 0.04 Ω 0.04 Ω 0.04 Ω
FET technology METAL-OXIDE SEMICONDUCTOR METAL-OXIDE SEMICONDUCTOR METAL-OXIDE SEMICONDUCTOR
JESD-30 code R-PDSO-G8 R-PDSO-G8 R-PDSO-G8
Number of components 2 2 2
Number of terminals 8 8 8
Operating mode ENHANCEMENT MODE ENHANCEMENT MODE ENHANCEMENT MODE
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
Package shape RECTANGULAR RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE
Polarity/channel type P-CHANNEL P-CHANNEL P-CHANNEL
Maximum pulsed drain current (IDM) 50 A 50 A 50 A
Certification status Not Qualified Not Qualified Not Qualified
surface mount YES YES YES
Terminal form GULL WING GULL WING GULL WING
Terminal location DUAL DUAL DUAL
transistor applications SWITCHING SWITCHING SWITCHING
Transistor component materials SILICON SILICON SILICON
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