)729F040B
4 Megabit (512 K x 8-Bit)
CMOS 5.0 Volt-only, Uniform Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
●
5.0 V
r
10% for read and write operations
—
MinimiVes
system level power requirements
●
Embedded Algorithms
— Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies bytes at specified addresses
●
Manufactured on 0.32 μm process technology
— Compatible with 0.5 μm
)729F040
device
●
High performance
— Access times as fast as
90
ns
●
Minimum 1,000,000 program/erase cycles per
sector guaranteed
20-year data retention at 125qC
— Reliable operation for the life of the system
●
Low power consumption
— 20 mA typical active read current
— 30 mA typical program/erase current
— 1 μA typical standby current (standard access
time to active mode)
●
Package options
— 32-pin PLCC, TSOP, or PDIP
— Please consult factory for Ceramic package options
●
Flexible sector architecture
— 8 uniform sectors of 64 Kbytes each
— Any combination of sectors can be erased
— Supports full chip erase
— Sector protection:
A hardware method of locking sectors to prevent
any program or erase operations within that sector
●
Compatible with JEDEC standards
— Pinout and software compatible with
single-power-supply Flash standard
— Superior inadvertent write protection
●
Data# Polling and toggle bits
— Provides a software method of detecting
program or erase cycle completion
●
Erase Suspend/Erase Resume
— Suspends a sector erase operation to read data
from, or program data to, a non-erasing sector,
then resumes the erase operation
Rev 1
1/33
2011
)729F040B
GENERAL DESCRIPTION
The
)729F040B
is a 4 Mbit, 5.0 volt-only Flash mem-
ory organiVed as 524,288 Kbytes of 8 bits each. The
512 Kbytes of data are divided into eight sectors of 64
Kbytes each for flexible erase capability. The 8 bits of
data appear on DQ0–DQ7. The
)729F040B
is offered
in 32-pin PLCC, TSOP, and PDIP packages. This device
is designed to be programmed in-system with the stan-
dard system 5.0 volt V
CC
supply. A 12.0 volt V
PP
is not
required for write or erase operations. The device can
also be programmed in standard EPROM programmers.
This device is manufactured using 0.32 μm pro-
cess technology, and offers all the features and
benefits of the
)729F040,
which was manufactured
using 0.5 μm process technology. In addtion, the
)729F040B
has a second toggle bit, DQ2, and also of-
fers the ability to program in the Erase Suspend mode.
The standard
)729F040B
offers access times of
90, 120, and 150 ns, allowing high-speed micropro-
cessors to operate without wait states. To eliminate bus
contention the device has separate chip enable (CE#),
write enable (WE#) and output enable (OE#) controls.
The device requires only a
single 5.0 volt power sup-
ply
for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard.
Com-
mands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write cy-
cles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the
Embedded
Program
algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the
Embedded Erase
algorithm—an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by reading the DQ7 (Data#
Polling) and DQ6 (toggle)
status bits.
After a program
or erase cycle has been completed, the device is ready
to read array data or accept another command.
The
sector erase architecture
allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The
hardware sector
protection
feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved via programming equipment.
The
Erase Suspend
feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The system can place the device into the
standby mode.
Power consumption is greatly reduced in this mode.
2XU
Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunneling.
The data is programmed using hot electron injection.
Rev 1
2/33
2011
)729F040B
PRODUCT SELECTOR GUIDE
Family Part Number
Speed Option
)7
29F040B
1$
V
CC
= 5.0 V
r
10%
-90
90
90
35
1$
-120
120
120
50
1$
-150
150
150
55
Max access time, ns (t
ACC
)
Max CE# access time, ns (t
CE
)
Max OE# access time, ns (t
OE
)
Note:
See the “AC Characteristics” section for more information.
BLOCK DIAGRAM
DQ0–DQ7
V
CC
V
SS
Erase Voltage
Generator
Input/Output
Buffers
WE#
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
STB
Data Latch
CE#
OE#
STB
V
CC
Detector
Timer
Address Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A0–A18
Rev 1
3/33
2011
)729F040B
CONNECTION DIAGRAMS
A18
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PDIP
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
WE#
V
CC
A12
A15
A16
A18
A17
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
4
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
5
6
7
8
9
10
11
12
13
3
2
1 32 31 30
29
28
27
26
25
24
23
22
21
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
PLCC
14 15 16 17 18 19 20
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
V
SS
DQ2
DQ1
DQ0
A0
A1
A2
A3
A11
A9
A8
A13
A14
A17
WE#
V
CC
A18
A16
A15
A12
A7
A6
A5
A4
V
SS
A11
A9
A8
A13
A14
A17
WE#
V
CC
A18
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32-Pin Standard TSOP
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
V
SS
DQ2
DQ1
DQ0
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32-Pin Reverse TSOP
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Rev 1
4/33
A17
WE#
2011
)729F040B
PIN CONFIGURATION
A0–A18
=
Address Inputs
Data Input/Output
Chip Enable
Write Enable
Output Enable
Device Ground
+5.0 V single power supply
(see Product Selector Guide for
device speed ratings and voltage
supply tolerances)
CE#
OE#
WE#
19
A0–A18
DQ0–DQ7
8
LOGIC SYMBOL
DQ0–DQ7 =
CE#
WE#
OE#
V
SS
V
CC
=
=
=
=
=
Rev 1
5/33
2011
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