HIGH-SPEED 3.3V
16K x 8 DUAL-PORT
STATIC RAM
Integrated Device Technology, Inc.
IDT70V06S/L
FEATURES:
• True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
• High-speed access
— Commercial:25/35/55ns (max.)
• Low-power operation
— IDT70V06S
Active: 350mW (typ.)
Standby: 3.5mW (typ.)
— IDT70V06L
Active: 350mW (typ.)
Standby: 1mW (typ.)
• IDT70V06 easily expands data bus width to 16 bits or
more using the Master/Slave select when cascading
more than one device
• M/
S
= H for
BUSY
output flag on Master
M/
S
= L for
BUSY
input on Slave
• Busy and Interrupt Flags
• On-chip port arbitration logic
• Full on-chip hardware support of semaphore signaling
between ports
• Fully asynchronous operation from either port
• Devices are capable of withstanding greater than 2001V
electrostatic discharge
• Battery backup operation—2V data retention
• LVTTL-compatible, single 3.3V (±0.3V) power supply
• Available in 68-pin PGA, 68-pin PLCC, and a 64-pin
TQFP
DESCRIPTION:
The IDT70V06 is a high-speed 16K x 8 Dual-Port Static
RAM. The IDT70V06 is designed to be used as a stand-alone
Dual-Port RAM or as a combination MASTER/SLAVE Dual-
Port RAM for 16-bit-or-more word systems. Using the IDT
MASTER/SLAVE Dual-Port RAM approach in 16-bit or wider
memory system applications results in full-speed, error-free
FUNCTIONAL BLOCK DIAGRAM
OE
L
R/
OE
R
R/
CE
L
W
L
CE
R
W
R
I/O
0L
- I/O
7L
I/O
Control
I/O
Control
I/O
0R
-I/O
7R
BUSY
L(1,2)
A
13L
A
0L
Address
Decoder
14
BUSY
R(1,2)
MEMORY
ARRAY
Address
Decoder
A
13R
A
0R
14
NOTES:
1. (MASTER):
BUSY
is output;
(SLAVE):
BUSY
is input.
2. BUSY outputs
and INT outputs
are non-tri-
stated push-pull.
OE
L
R/
CE
L
W
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
R/
OE
R
W
R
SEM
R
(2)
SEM
L
INT
L
(2)
M/
S
INT
R
2942 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©1996 Integrated Device Technology, Inc.
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
OCTOBER 1996
DSC-2942/4
6.36
1
IDT70V06S/L
HIGH-SPEED 3.3V 16K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
operation without the need for additional discrete logic.
This device provides two independent ports with separate
control, address, and I/O pins that permit independent,
asynchronous access for reads or writes to any location in
memory. An automatic power down feature controlled by
CE
permits the on-chip circuitry of each port to enter a very low
standby power mode.
Fabricated using IDT’s CMOS high-performance technol-
ogy, these devices typically operate on only 350mW of power.
Low-power (L) versions offer battery backup data retention
capability with typical power consumption of 500µW from a 2V
battery.
The IDT70V06 is packaged in a ceramic 68-pin PGA, a 68-
pin PLCC, and a 64-pin thin plastic quad flatpack (TQFP).
PIN CONFIGURATIONS
(1,2)
I/O
1L
I/O
0L
N/C
SEM
L
4
W
L
R/
5
INDEX
I/O
2L
I/O
3L
I/O
4L
I/O
5L
GND
I/O
6L
I/O
7L
V
CC
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
9
8
7
6
3
N/C
A
13L
V
CC
A
12L
A
11L
A
10L
A
9L
A
8L
A
7L
A
6L
2
1 68 67 66 65 64 63 62 61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
OE
L
CE
L
IDT70V06
J68-1
F68-1
PLCC / FLATPACK
TOP VIEW(3)
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
GND
M/
S
INT
R
BUSY
R
A
0R
A
1R
A
2R
A
3R
A
4R
2942 drw 02
44
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
I/O
7R
N/C
SEM
R
N/C
A
13R
GND
A
12R
A
11R
A
10R
A
9R
A
8R
A
7R
A
6R
A
5R
OE
R
W
R
CE
R
I/O
1L
I/O
0L
R/
L
SEM
L
A
12L
A
11L
A
10L
A
9L
A
8L
56
55
CE
L
A
13L
V
CC
OE
L
R/
W
INDEX
64
59
58
63
62
60
57
52
51
29
30
19
22
25
28
31
32
20
21
26
27
17
18
23
24
I/O
2L
I/O
3L
I/O
4L
I/O
5L
GND
I/O
6L
I/O
7L
V
CC
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
61
54
53
50
49
A
7L
A
6L
A
5L
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
IDT70V06
PN-64
TQFP
TOP VIEW(3)
BUSY
L
GND
M/
S
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
I/O
6R
I/O
7R
SEM
R
A
12R
R/
R
A
11R
A
10R
CE
R
A
7R
OE
R
A
8R
NOTES:
1. All Vcc pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. This text does not indicate the actual part marking.
6.36
A
13R
GND
A
9R
A
6R
A
5R
W
2942 drw 03
2
IDT70V06S/L
HIGH-SPEED 3.3V 16K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS (CONT'D)
(1,2)
51
11
53
A
7L
55
A
9L
A
5L
52
A
6L
54
A
8L
50
A
4L
49
A
3L
48
A
2L
47
A
1L
46
44
42
A
0L
BUSY
L
M/
S
45
40
38
A
1R
INT
R
36
A
3R
35
A
4R
32
A
7R
30
A
9R
34
A
5R
33
A
6R
31
A
8R
10
43
41
39
37
INT
L
GND
BUSY
R
A
0R
A
2R
09
08
56
57
A
11L
A
10L
58
59
07 V
CC
A
12L
60
61
06
N/C A
13L
63
05
IDT70V06
G68-1
68-PIN PGA
TOP VIEW(3)
29
28
A
11R
A
10R
27
26
GND A
12R
24
N/C
25
A
13R
23
SEM
L
CE
L
OE
L
R/
W
L
64
62
65
04
SEM
R
20
22
CE
R
67
66
03 I/O
0L
N/C
02
1
3
68
I/O
1L
I/O
2L
I/O
4L
2
01
A
INDEX
NOTES:
1. All V
CC
pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. This text does not indicate the actual part marking.
OE
R
21
R/
R
W
5
7
9
11
13
15
GND I/O
7L
GND I/O
1R
V
CC
I/O
4R
6
8
10
12
14
16
I/O
6L
V
CC
I/O
0R
I/O
2R
I/O
3R
I/O
5R
D
E
F
G
H
J
18
19
I/O
7R
N/C
17
I/O
6R
K
L
2942
drw 04
4
I/O
3L
I/O
5L
B
C
PIN NAMES
Left Port
Right Port
Names
Chip Enable
Read/Write Enable
Output Enable
Address
Data Input/Output
Semaphore Enable
Interrupt Flag
Busy Flag
Master or Slave Select
Power
Ground
2942 tbl 01
CE
L
R/
W
L
OE
L
A
0L
– A
13L
I/O
0L
– I/O
7L
CE
R
R/
W
R
OE
R
A
0R
– A
13R
I/O
0R
– I/O
7R
SEM
L
INT
L
BUSY
L
M/
S
V
CC
SEM
R
INT
R
BUSY
R
GND
6.36
3
IDT70V06S/L
HIGH-SPEED 3.3V 16K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
TRUTH TABLE I – NON-CONTENTION READ/WRITE CONTROL
Inputs
(1)
Outputs
CE
H
L
L
X
NOTE:
R/
W
X
L
H
X
OE
X
X
L
H
SEM
H
H
H
X
I/O
0-7
High-Z
DATA
IN
DATA
OUT
High-Z
Deselected: Power Down
Write to Memory
Read Memory
Outputs Disabled
Mode
2942 tbl 02
1. A
0L
— A
13L
≠
A
0R
— A
13R.
TRUTH TABLE II – SEMAPHORE READ/WRITE CONTROL
(1)
Inputs
Outputs
CE
H
H
L
R/
W
H
X
OE
L
X
X
SEM
L
L
L
I/O
0-7
DATA
OUT
DATA
IN
—
Read Data in Semaphore Flag
Write D
IN0
into Semaphore Flag
Not Allowed
Mode
NOTE:
1. There are eight semaphore flags written to via I/O
0
and read from all I/O's (I/O
0
-I/O
7
). These eight semaphores are addressed by A
0
- A
2
.
2942 tbl 03
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
(2)
Rating
Terminal Voltage
with Respect
to GND
Operating
Temperature
Temperature
Under Bias
Storage
Temperature
DC Output
Current
Commercial Unit
–0.5 to +4.6
V
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Commercial
Ambient
Temperature
0°C to +70°C
GND
0V
V
CC
3.3V
±
0.3V
2942 tbl 05
T
A
T
BIAS
T
STG
I
OUT
0 to +70
–55 to +125
–55 to +125
50
°C
°C
°C
mA
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
V
CC
GND
V
IH
V
IL
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Min.
3.0
0
2.0
-0.3
(1)
Typ.
3.3
0
—
—
Max. Unit
3.6
0
Vcc+0.3
0.8
V
V
V
V
2942 tbl 06
NOTES:
2942 tbl 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. V
TERM
must not exceed Vcc + 0.3V.
NOTES:
1. V
IL
≥
-1.5V for pulse width less than 10ns.
2. V
TERM
must not exceed Vcc + 0.5V.
CAPACITANCE
(1)
(T
A
= +25°C, f = 1.0MHz)TQFP ONLY
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output
Capacitance
Conditions
(1)
Max.
V
IN
= 3dV
V
OUT
= 3dV
11
11
Unit
pF
pF
NOTES:
2942 tbl 07
1. This parameter is determined by device characterization but is not
production tested.
2. 3dV represents the interpolated capacitance when the input and output
signals switch from 0V to 3V or from 3V to 0V.
6.36
4
IDT70V06S/L
HIGH-SPEED 3.3V 16K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(V
CC
= 3.3V
±
0.3V)
IDT70V06S
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Input Leakage Current
(1)
Output Leakage Current
Output Low Voltage
Output High Voltage
Test Conditions
V
CC
= 3.6V, V
IN
= 0V to V
CC
Min.
—
—
—
2.4
Max.
10
10
0.4
—
IDT70V06L
Min.
—
—
—
2.4
Max.
5
5
0.4
—
Unit
µA
µA
V
V
2942 tbl 08
CE
= V
IH
, V
OUT
= 0V to V
CC
I
OL
= 4mA
I
OH
= -4mA
NOTE:
1. At Vcc
≤
2.0V input leakages are undefined.
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(1)
(V
CC
= 3.3V
±
0.3V)
70V06X25
Symbol
Parameter
Dynamic Operating
I
CC
Current
(Both Ports Active)
I
SB1
Standby Current
(Both Ports — TTL
Level Inputs)
Standby Current
(One Port — TTL
Level Inputs)
Full Standby Current
(Both Ports — All
CMOS Level Inputs)
Test
Condition
CE
= V
IL
, Outputs Open
SEM
= V
IH
f = f
MAX(3)
70V06X35
70V06X55
Version
Typ.
(2)
Max. Typ.
(2)
COM’L. S
80
140
70
L
70
120
60
COM’L. S
L
COM’L. S
L
12
10
40
30
25
20
82
72
10
8
35
25
Max. Typ.
(2)
Max. Unit
115
70
115 mA
100
60
100
25
20
72
62
10
8
35
25
25
20
72
62
mA
f = f
MAX(3)
CE
R
=
CE
L
= V
IH
SEM
R
=
SEM
L
= V
IH
CE
L
or
CE
R
= V
IH
I
SB2
mA
Active Port Outputs Open
f = f
MAX(3)
SEM
R
=
SEM
L
= V
IH
I
SB3
Both Ports
CE
L
and
CE
R
≥
V
CC
- 0.2V
V
IN
≥
V
CC
- 0.2V or
V
IN
≤
0.2V, f = 0
(4)
SEM
R
=
SEM
L
≥
V
CC
- 0.2V
COM’L. S
L
1.0
0.2
5
2.5
1.0
0.2
5
2.5
1.0
0.2
5
2.5
mA
I
SB4
Full Standby Current
(One Port — All
CMOS Level Inputs)
One Port
CE
L
or
CE
R
≥
V
CC
- 0.2V
SEM
R
=
SEM
L
≥
V
CC
- 0.2V
V
IN
≥
V
CC
- 0.2V or V
IN
≤
0.2V
Active Port Outputs Open
f = f
MAX(3)
COM’L. S
L
50
40
81
71
45
35
71
61
45
35
71
61
mA
NOTES:
2942 tbl 09
1. "X" in part numbers indicates power rating (S or L).
2. V
CC
= 3.3V, T
A
= +25°C.
3. At f = f
MAX
,
address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/t
RC
, and using “AC Test Conditions”
of input levels of GND to 3V.
4. f = 0 means no address or control lines change.
6.36
5
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