4Gb DDR3 SDRAM
4Gb DDR3L SDRAM
Lead-Free&Halogen-Free
(RoHS Compliant)
H5TC4G83CFR-xxA
H5TC4G83CFR-xxI
H5TC4G83CFR-xxL
H5TC4G83CFR-xxJ
H5TC4G63CFR-xxA
H5TC4G63CFR-xxI
H5TC4G63CFR-xxL
H5TC4G63CFR-xxJ
* SK Hynix reserves the right to change products or specifications without notice.
Rev. 1.1 Dec. 2014
1
Revision History
Revision No.
0.1
0.2
0.3
1.0
1.1
History
Initial Version
Operating Frequency Modified
x16 IDD Update &
Input/Output capacitance Tyop Correction
Official Vesion with IDD Spec
Tyop Correction
Draft Date
Feb. 2014
July. 2014
July. 2014
Oct. 2014
Dec. 2014
Page 4.
*Note1
Page 25,26
Page 25
Page 8
Remark
Rev. 1.1/ Dec. 2014
2
Description
The H5TC4G83CFR-xxA(I,L,J),H5TQC4G63CFR-xxA(I,L,J) are a 4Gb low power Double Data Rate III
(DDR3L) Synchronous DRAM, ideally suited for the main memory applications which requires large
memory density, high bandwidth and low power operation at 1.35V. SK Hynix DDR3L SDRAM provides
backward compatibility with the 1.5V DDR3 based environment without any changes. SK Hynix 4Gb DDR3L
SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While
all addresses and control inputs are latched on the rising edges of the clock (falling edges of the clock),
data, data strobes and write data masks inputs are sampled on both rising and falling edges of it. The data
paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth.
Device Features and Ordering Information
FEATURES
• VDD=VDDQ=1.35V + 0.100 / - 0.067V
• Fully differential clock inputs (CK, CK) operation
• Differential Data Strobe (DQS, DQS)
• On chip DLL align DQ, DQS and DQS transition with CK
transition
• DM masks write data-in at the both rising and falling
edges of the data strobe
• All addresses and control inputs except data,
data strobes and data masks latched on the
rising edges of the clock
• 8banks
• Average Refresh Cycle (Tcase of
0
o
C~ 95
o
C)
- 7.8 µs at
0
o
C ~ 85
o
C
- 3.9
µs at 85
o
C ~ 95
o
C
Commercial Temperature(
0
o
C ~ 95
o
C)
Industrial Temperature(
-40
o
C ~ 95
o
C)
• JEDEC standard 78ball FBGA(x8), 96ball FBGA (x16)
• Driver strength selected by EMRS
• Dynamic On Die Termination supported
• Programmable CAS latency 5, 6, 7, 8, 9, 10, 11 and 13 • Asynchronous RESET pin supported
supported
• ZQ calibration supported
• Programmable additive latency 0, CL-1, and CL-2
supported
• Programmable CAS Write latency (CWL) = 5, 6, 7, 8
• Programmable burst length 4/8 with both nibble
sequential and interleave mode
• BL switch on the fly
• TDQS (Termination Data Strobe) supported (x8 only)
• Write Levelization supported
• 8 bit pre-fetch
* This product in compliance with the RoHS directive.
Rev. 1.1/ Dec. 2014
3
ORDERING INFORMATION
Part No.
H5TC4G83CFR-*xxA
H5TC4G83CFR-*xxI
H5TC4G83CFR-*xxL
H5TC4G83CFR-*xxJ
H5TC4G63CFR-*xxA
H5TC4G63CFR-*xxI
H5TC4G63CFR-*xxL
H5TC4G63CFR-*xxJ
256M x 16
Low Power Consumption
(IDD6 Only)
512M x 8
Low Power Consumption
(IDD6 Only)
Normal Consumption
Configuration
Power Consumption
Normal Consumption
Temperature
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
96ball FBGA
78ball FBGA
Package
* xx means Speed Bin Grade
OPERATING FREQUENCY
Speed
Grade
(Marking)
-H9
-PB
-RD*
Frequency [Mbps]
CL5
667
667
CL6
800
800
800
CL7
1066
1066
1066
CL8
1066
1066
1066
CL9
1333
1333
1333
CL10
1333
1333
1333
1600
1600
1866
CL11
CL12
CL13
CL14
Remark
(CL-tRCD-tRP)
DDR3-1333 9-9-9
DDR3-1600 11-11-11
DDR3-1866 13-13-13
*Note1:
-RD covers lower speed of -PB and -H9.
Rev. 1.1/ Dec. 2014
4
x8 Package Ball out (Top view): 78ball FBGA Package
1
A
B
C
D
E
F
G
H
J
K
L
M
N
VSS
VSS
VDDQ
VSSQ
VREFDQ
NC
ODT
NC
VSS
VDD
VSS
VDD
VSS
1
2
VDD
VSSQ
DQ2
DQ6
VDDQ
VSS
VDD
CS
BA0
A3
A5
A7
RESET
2
3
NC
DQ0
DQS
DQS
DQ4
RAS
CAS
WE
BA2
A0
A2
A9
A13
3
4
5
6
4
5
6
7
NF/TDQS
DM/TDQS
DQ1
VDD
DQ7
CK
CK
A10/AP
A15
A12/BC
A1
A11
A14
7
8
VSS
VSSQ
DQ3
VSS
DQ5
VSS
VDD
ZQ
VREFCA
BA1
A4
A6
A8
8
9
VDD
VDDQ
VSSQ
VSSQ
VDDQ
NC
CKE
NC
VSS
VDD
VSS
VDD
VSS
9
A
B
C
D
E
F
G
H
J
K
L
M
N
1 2 3
A
B
C
D
E
F
G
H
J
K
L
M
N
7 8 9
(Top View: See the balls through the Package)
Populated ball
Ball not populated
Rev. 1.1/ Dec. 2014
5
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