HU82563EB datasheet, PDF - EEWORLD Datasheet

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HU82563EB: DescriptionInterface Circuit, 2-Trnsvr, PQFP100, 14 X 14 MM, TQFP-100; CategoryWireless rf/communication Telecom circuit; File Size567KB，52 Pages; ManufacturerIntel; Websitehttp://www.intel.com/

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HU82563EB Overview

Interface Circuit, 2-Trnsvr, PQFP100, 14 X 14 MM, TQFP-100

HU82563EB Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Intel
Parts packaging code	QFP
package instruction	HTFQFP, TQFP100,.63SQ
Contacts	100
Reach Compliance Code	compliant
data rate	1000000 Mbps
JESD-30 code	S-PQFP-G100
JESD-609 code	e0
length	14 mm
Number of functions	1
Number of terminals	100
Transceiver quantity	2
Maximum operating temperature	60 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	HTFQFP
Encapsulate equivalent code	TQFP100,.63SQ
Package shape	SQUARE
Package form	FLATPACK, HEAT SINK/SLUG, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	240
power supply	1.2,1.9,3.3 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
Nominal supply voltage	3.3 V
surface mount	YES
Telecom integrated circuit types	INTERFACE CIRCUIT
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	14 mm

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82563EB/82564EB Gigabit Platform LAN

Connect

Networking Silicon

Datasheet

Product Features

■

IEEE 802.3ab compliant

— Robust operation over the installed base of

Category-5 (Cat-5) twisted pair cabling

PICMG 3.1 compliant

— Robust operation in backplane over

Ethernet applications.

Support for cable line lengths greater than

100 m (spec); 123 m physical

— Robust end to end connections over

various cable lengths

Full duplex at 10, 100, or 1000 Mb/s and half

duplex at 10 or 100 Mb/s.

IEEE 802.3ab Auto-negotiation with Next

Page support

— Automatic link configuration including

speed, duplex, and flow control

10/100 downshift

— Automatic link speed adjustment with

poor quality cable

Automatic MDI crossover

— Helps to correct for infrastructure issues

Advanced Cable Diagnostics

— Improved end-user troubleshooting

Kumeran interface

— Low pin count, high speed interface to the

Intel® 631xESB/632xESB I/O Controller

Hub

■

— Allows PHY placement proximity to I/O

back panel.

7 LED outputs per port (4 configurable plus 3

dedicated)

— Link and Activity indications (10, 100,

1000 Mb/s) on each port

Clock supplied to the 631xESB/632xESB

— Cost optimized design

Full chip power down

— Support for lowest power state

100 pin TQFP Package

— Smaller footprint and lower power

dissipation compared to multi-chip MAC

and PHY solutions

Operating temperature: 0°C to 60° C

(maximum) – heat sink or forced airflow not

required

— Simple thermal design

Power Consumption: < 1.0 Watts per port

(silicon power)

— Minimize impact of incorporating dual

Gigabit instead of Fast Ethernet

Leaded and lead-free

100-pin TQFL with an

Exposed-Pad*. Devices that are lead-free are

marked with a circled “e3” and have a

product code: HYXXXXX

a.This device is lead-free. That is, lead has not been intentionally added, but lead may still exist as an impurity at <1000 ppm.

The Material Declaration Data Sheet, which includes lead impurity levels and the concentration of other Restriction on Hazard-

ous Substances (RoHS) -banned materials, is available at:

ftp://download.intel.com/design/packtech/material_content_IC_Pack

In addition, this device has been tested and conforms to the same parametric specifications as previous versions of the device.

For more information regarding lead-free products from Intel Corporation, contact your Intel Field Sales representative.

316534-004

Revision 2.9

82563EB/82564EB Gigabit Platform LAN Connect Networking Silicon

Revision History

Date

Nov 2007

Oct 2007

April 2007

Feb 2007

May 2006

April 2006

Revision

2.9

2.8

2.7

2.6

2.5

2.1

Comments

Updated Tables 19, 20, 23, and 24. Updated Figures 5

and 6.

Updated Table 16 “Recommended Operating Conditions”.

Updated Section 4.2, Table 16 “Core Digital Voltage

Range”.

Updated Table 6.

Initial public release.

Removed “Preliminary” from section 4.9 “Power

Consumption”.

Updated 1.9V external power supply parameters in Tables

16 and 19.

Nov 2005

Aug 2005

2.0

1.75

Initial release (Intel Confidential).

Added lead-free information.

Added measured power consumption values.

Updated crystal specifications (drive level now 750

µW).

Changed 1.8V power rail references to 1.9V.

Dec 2004

Sep 2004

Jul 2004

May 2004

1.0

0.70

0.51

0.5

Major revisions in all sections.

Added power sequencing.

Changed pin 51 (page13) from AVDD (1.8V) to AVDDR

(3.3V).

Initial release (Intel Secret).

Legal Notice

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY

ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN

INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS

ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES

RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER

INTELLECTUAL PROPERTY RIGHT.

Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

This document contains information on products in the design phase of development. The information here is subject to change without notice. Do not

finalize a design with this information.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The 82563EB/82564EB Gigabit Platform LAN Connects discussed in this document may contain design defects or errors known as errata which may

cause the product to deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from:

Intel Corporation

P.O. Box 5937

Denver, CO 80217-9808

or call in North America 1-800-548-4725, Europe 44-0-1793-431-155, France 44-0-1793-421-777, Germany 44-0-1793-421-333, other Countries 708-

296-9333.

Intel® is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries.

*Other names and brands may be claimed as the property of others.

82563EB/82564EB Gigabit Platform LAN Connect Networking Silicon

Contents

1.0

Introduction......................................................................................................................... 1

1.1

1.2

1.3

2.0

3.0

Document Scope................................................................................................... 1

Reference Documents...........................................................................................1

Product Codes....................................................................................................... 2

Block Diagrams .................................................................................................................. 3

Signal Descriptions............................................................................................................. 5

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.9

3.10

3.11

3.12

3.13

3.14

3.15

Signal Type Definitions.......................................................................................... 5

Shared PHY Pins .................................................................................................. 6

MDIO Interface ...................................................................................................... 6

Port A PHY Interface ............................................................................................. 7

Port A Kumeran Interface...................................................................................... 8

Port A LEDs........................................................................................................... 8

Reset, Power Down, and Initialization Signals ...................................................... 9

JTAG and IEEE Interface ...................................................................................... 9

Reserved Signals ................................................................................................10

Voltage Control Pins............................................................................................10

Clock Generator Interface ...................................................................................11

Power/Ground Pins .............................................................................................11

Port B PHY Interface ...........................................................................................13

Port B Kumeran Interface....................................................................................14

Port B LEDs.........................................................................................................15

Absolute Maximum Ratings.................................................................................17

Recommended Operating Conditions .................................................................17

DC and AC Characteristics .................................................................................17

Power Supply Connections .................................................................................18

4.4.1 External LVR Power Delivery .................................................................18

4.4.2 Power Sequencing with External Regulators .........................................20

4.4.3 Internally-Generated Power Delivery .....................................................21

4.4.4 Internal LVR Power Sequencing ............................................................22

Link (MDI) Interface.............................................................................................26

Kumeran (Serial) Interface ..................................................................................27

4.6.1 Transmit .................................................................................................27

4.6.2 Receive ..................................................................................................28

4.6.3 Electrical Idle ..........................................................................................29

Crystal ................................................................................................................31

4.7.1 External Clock Oscillator .......................................................................31

Reset and Initial Clock Timing.............................................................................32

Power Consumption ............................................................................................33

Package Information ...........................................................................................37

Thermal Specifications ........................................................................................39

Pinout Information ...............................................................................................40

4.0

Voltage, Temperature and Timing Specifications.............................................................17

4.1

4.2

4.3

4.4

4.5

4.6

4.7

4.8

4.9

5.0

5.1

5.2

5.3

Package and Pinout Information ......................................................................................37

iii

82563EB/82564EB Gigabit Platform LAN Connect Networking Silicon

5.4

5.5

Interface Diagrams.............................................................................................. 43

Visual Pin Assignments....................................................................................... 44

Figures

82563EB Dual Port Block Diagram ....................................................................... 3

82564EB Single Port Block Diagram .................................................................... 3

82563EB/82564EB power up sequencing with external regulators .................... 21

82563EB/82564EB power up sequencing with internal regulators ..................... 23

82563EB 1.9V and 1.2V internal LVR schematic................................................ 26

82564EB 1.9V and 1.2V internal LVR schematic............................................... 26

Kumeran (Serial) Transmit Eye Diagram ............................................................ 28

Kumeran (Serial) Receive Eye Diagram ............................................................. 29

External Clock Oscillator Connectivity to 82563EB/82564EB............................. 31

82563EB/82564EB Reset Timing ....................................................................... 32

Mechanical Information ....................................................................................... 37

Mechanical Specifications and Notes ................................................................. 38

82563EB/82564EB Interfaces............................................................................. 43

82563EB Dual Port Gigabit Platform LAN connect Pinout (Top View) ............... 44

82564EB Single Port Gigabit Platform LAN Connect Pinout (Top View) ............ 45

Tables

Product Ordering Codes ....................................................................................... 2

Shared PHY Pins .................................................................................................. 6

MDIO Interface Pins.............................................................................................. 6

Port A PHY Interface Pins..................................................................................... 7

Port A Kumeran Interface Pins.............................................................................. 8

Port A LEDs .......................................................................................................... 8

Reset and Power Down Signals............................................................................ 9

JTAG Signals ........................................................................................................ 9

Test Signals ........................................................................................................ 10

Voltage Control Pins ........................................................................................... 10

Clock Generator Related Signals........................................................................ 11

Power/Ground Pins ............................................................................................. 11

Port B PHY Interface Pins................................................................................... 13

Port B Kumeran Interface Pins............................................................................ 14

Port B LEDs ........................................................................................................ 15

Absolute Maximum Ratings ............................................................................... 17

Recommended Operating Conditions ................................................................. 17

DC and AC Characteristics ................................................................................. 17

3.3V External Power Supply Parameters ............................................................ 19

1.9V External Power Supply Parameters ............................................................ 19

1.2V External Power Supply Parameters ............................................................ 20

3.3V External Power Supply Parameters........................................................... 21

82563EB/82564EB BOM (Bill of

Material) of Components for Internal Regulator .................................................. 23

1.9V Internal LVR Specification .......................................................................... 24

1.2V Internal LVR Specification .......................................................................... 24

PNP Specification ............................................................................................... 25

Link (MDI) Interface Electrical Specification........................................................ 26

Kumeran (Serial) Transmit Specifications ........................................................... 27

HU82563EB Related Products

	HU82563EB	HY82563EB/SL7WG	HU82564EB
Description	Interface Circuit, 2-Trnsvr, PQFP100, 14 X 14 MM, TQFP-100	Ethernet Transceiver, 2-Trnsvr, PQFP100,	Interface Circuit, 1-Trnsvr, PQFP100, 14 X 14 MM, TQFP-100
Is it Rohs certified?	incompatible	conform to	incompatible
Reach Compliance Code	compliant	unknown	compliant
data rate	1000000 Mbps	1000000 Mbps	1000000 Mbps
JESD-30 code	S-PQFP-G100	S-PQFP-G100	S-PQFP-G100
Number of terminals	100	100	100
Transceiver quantity	2	2	1
Maximum operating temperature	60 °C	60 °C	60 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	HTFQFP	QFP	HTFQFP
Encapsulate equivalent code	TQFP100,.63SQ	TQFP100,.63SQ	TQFP100,.63SQ
Package shape	SQUARE	SQUARE	SQUARE
Package form	FLATPACK, HEAT SINK/SLUG, THIN PROFILE, FINE PITCH	FLATPACK	FLATPACK, HEAT SINK/SLUG, THIN PROFILE, FINE PITCH
power supply	1.2,1.9,3.3 V	1.2,1.9,3.3 V	1.2,1.9,3.3 V
Certification status	Not Qualified	Not Qualified	Not Qualified
surface mount	YES	YES	YES
Telecom integrated circuit types	INTERFACE CIRCUIT	ETHERNET TRANSCEIVER	INTERFACE CIRCUIT
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	GULL WING	GULL WING	GULL WING
Terminal pitch	0.5 mm	0.5 mm	0.5 mm
Terminal location	QUAD	QUAD	QUAD
Is it lead-free?	Contains lead	-	Contains lead
Maker	Intel	-	Intel
Parts packaging code	QFP	-	QFP
package instruction	HTFQFP, TQFP100,.63SQ	-	HTFQFP, TQFP100,.63SQ
Contacts	100	-	100
JESD-609 code	e0	-	e0
length	14 mm	-	14 mm
Number of functions	1	-	1
Peak Reflow Temperature (Celsius)	240	-	240
Maximum seat height	1.2 mm	-	1.2 mm
Nominal supply voltage	3.3 V	-	3.3 V
Terminal surface	TIN LEAD	-	TIN LEAD
Maximum time at peak reflow temperature	30	-	30
width	14 mm	-	14 mm

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