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74AUP1T98GF

Description
Logic Circuit, CMOS, PDSO6
Categorylogic    logic   
File Size131KB,20 Pages
ManufacturerNexperia
Websitehttps://www.nexperia.com
Environmental Compliance
Download Datasheet Parametric Compare View All

74AUP1T98GF Overview

Logic Circuit, CMOS, PDSO6

74AUP1T98GF Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerNexperia
package instructionVSON,
Reach Compliance Codecompliant
seriesAUP/ULP/V
JESD-30 codeS-PDSO-N6
JESD-609 codee3
length1 mm
Logic integrated circuit typeLOGIC CIRCUIT
Humidity sensitivity level1
Number of functions1
Number of terminals6
Maximum operating temperature125 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeVSON
Package shapeSQUARE
Package formSMALL OUTLINE, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)260
Certification statusNot Qualified
Maximum seat height0.5 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)2.3 V
Nominal supply voltage (Vsup)3 V
surface mountYES
technologyCMOS
Temperature levelAUTOMOTIVE
Terminal surfaceTin (Sn)
Terminal formNO LEAD
Terminal pitch0.35 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width1 mm
74AUP1T98
Low-power configurable gate with voltage-level translator
Rev. 3 — 30 November 2011
Product data sheet
1. General description
The 74AUP1T98 provides low-power, low-voltage configurable logic gate functions. The
output state is determined by eight patterns of 3-bit input. The user can choose the logic
functions MUX, AND, OR, NAND, NOR, inverter and buffer. All inputs can be connected to
V
CC
or GND.
This device ensures a very low static and dynamic power consumption across the entire
V
CC
range from 2.3 V to 3.6 V.
The 74AUP1T98 is designed for logic-level translation applications with input switching
levels that accept 1.8 V low-voltage CMOS signals, while operating from either a single
2.5 V or 3.3 V supply voltage.
The wide supply voltage range ensures normal operation as battery voltage drops from
3.6 V to 2.3 V.
This device is fully specified for partial power-down applications using I
OFF
.
The I
OFF
circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
Schmitt trigger inputs make the circuit tolerant to slower input rise and fall times across
the entire V
CC
range.
2. Features and benefits
Wide supply voltage range from 2.3 V to 3.6 V
High noise immunity
ESD protection:
HBM JESD22-A114F Class 3A exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Low static power consumption; I
CC
= 1.5
A
(maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V
CC
I
OFF
circuitry provides partial power-down mode operation
Multiple package options
Specified from
40 C
to +85
C
and
40 C
to +125
C

74AUP1T98GF Related Products

74AUP1T98GF 74AUP1T98GM 74AUP1T98GN 74AUP1T98GS 74AUP1T98GW
Description Logic Circuit, CMOS, PDSO6 Logic Circuit, CMOS, PDSO6 Logic Circuit, CMOS, PDSO6 Logic Circuit, CMOS, PDSO6 Logic Circuit, CMOS, PDSO6
Is it Rohs certified? conform to conform to conform to conform to conform to
Maker Nexperia Nexperia Nexperia Nexperia Nexperia
package instruction VSON, VSON, SON, VSON, TSSOP,
Reach Compliance Code compliant compliant compliant compliant compliant
series AUP/ULP/V AUP/ULP/V AUP/ULP/V AUP/ULP/V AUP/ULP/V
JESD-30 code S-PDSO-N6 S-PDSO-N6 R-PDSO-N6 S-PDSO-N6 R-PDSO-G6
JESD-609 code e3 e3 e3 e3 e3
length 1 mm 1.45 mm 1 mm 1 mm 2 mm
Logic integrated circuit type LOGIC CIRCUIT LOGIC CIRCUIT LOGIC CIRCUIT LOGIC CIRCUIT LOGIC CIRCUIT
Humidity sensitivity level 1 1 1 1 1
Number of functions 1 1 1 1 1
Number of terminals 6 6 6 6 6
Maximum operating temperature 125 °C 125 °C 125 °C 125 °C 125 °C
Minimum operating temperature -40 °C -40 °C -40 °C -40 °C -40 °C
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code VSON VSON SON VSON TSSOP
Package shape SQUARE SQUARE RECTANGULAR SQUARE RECTANGULAR
Package form SMALL OUTLINE, VERY THIN PROFILE SMALL OUTLINE, VERY THIN PROFILE SMALL OUTLINE SMALL OUTLINE, VERY THIN PROFILE SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius) 260 260 260 260 260
Certification status Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
Maximum seat height 0.5 mm 0.5 mm 0.35 mm 0.35 mm 1.1 mm
Maximum supply voltage (Vsup) 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V
Minimum supply voltage (Vsup) 2.3 V 2.3 V 2.3 V 2.3 V 2.3 V
Nominal supply voltage (Vsup) 3 V 3 V 3 V 3 V 3 V
surface mount YES YES YES YES YES
technology CMOS CMOS CMOS CMOS CMOS
Temperature level AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE
Terminal surface Tin (Sn) Tin (Sn) Tin (Sn) Tin (Sn) Tin (Sn)
Terminal form NO LEAD NO LEAD NO LEAD NO LEAD GULL WING
Terminal pitch 0.35 mm 0.5 mm 0.3 mm 0.35 mm 0.65 mm
Terminal location DUAL DUAL DUAL DUAL DUAL
Maximum time at peak reflow temperature 30 30 30 30 30
width 1 mm 1 mm 0.9 mm 1 mm 1.25 mm
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