74LVC1G175GW-Q100 datasheet, PDF

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74LVC1G175GW-Q100: DescriptionD Flip-Flop, LVC/LCX/Z Series, 1-Func, Positive Edge Triggered, 1-Bit, True Output, CMOS, PDSO6; Categorylogic logic; File Size113KB，16 Pages; ManufacturerNexperia; Websitehttps://www.nexperia.com; Environmental Compliance

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74LVC1G175GW-Q100 Overview

D Flip-Flop, LVC/LCX/Z Series, 1-Func, Positive Edge Triggered, 1-Bit, True Output, CMOS, PDSO6

74LVC1G175GW-Q100 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Nexperia
package instruction	SC-88,6 PIN
Reach Compliance Code	compliant
series	LVC/LCX/Z
JESD-30 code	R-PDSO-G6
JESD-609 code	e3
length	2 mm
Logic integrated circuit type	D FLIP-FLOP
Humidity sensitivity level	1
Number of digits	1
Number of functions	1
Number of terminals	6
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	260
propagation delay (tpd)	17 ns
Filter level	AEC-Q100
Maximum seat height	1.1 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	1.65 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal surface	Tin (Sn)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
Trigger type	POSITIVE EDGE
width	1.25 mm
minfmax	200 MHz

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74LVC1G175-Q100

Single D-type flip-flop with reset; positive-edge trigger

Rev. 1 — 15 November 2013

Product data sheet

1. General description

The 74LVC1G175-Q100 is a low-power, low-voltage single positive edge triggered D-type

flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q

output. The master reset (MR) is an asynchronous active LOW input and operates

independently of the clock input. Information on the data input is transferred to the

Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable

one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. The

inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this

device in a mixed 3.3 V and 5 V environment. This device is fully specified for partial

power-down applications using I

OFF

. The I

OFF

circuitry disables the output, preventing the

damaging backflow current through the device when it is powered down. Schmitt trigger

action at all inputs makes the circuit highly tolerant of slower input rise and fall times.

This product has been qualified to the Automotive Electronics Council (AEC) standard

Q100 (Grade 1) and is suitable for use in automotive applications.

2. Features and benefits



Automotive product qualification in accordance with AEC-Q100 (Grade 1)



Specified from

40 C

to +85

C

and from

40 C

to +125

C



Wide supply voltage range from 1.65 V to 5.5 V



5 V tolerant inputs for interfacing with 5 V logic



High noise immunity



Complies with JEDEC standard:



JESD8-7 (1.65 V to 1.95 V)



JESD8-5 (2.3 V to 2.7 V)



JESD8B/JESD36 (2.7 V to 3.6 V).



24

mA output drive (V

= 3.0 V)



CMOS low power consumption



Latch-up performance exceeds 250 mA



Direct interface with TTL levels



Inputs accept voltages up to 5 V



Multiple package options



ESD protection:



MIL-STD-883, method 3015 exceeds 2000 V



HBM JESD22-A114F exceeds 2000 V



MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0

)

74LVC1G175GW-Q100 Related Products

	74LVC1G175GW-Q100	74LVC1G175GV-Q100
Description	D Flip-Flop, LVC/LCX/Z Series, 1-Func, Positive Edge Triggered, 1-Bit, True Output, CMOS, PDSO6	D Flip-Flop, LVC/LCX/Z Series, 1-Func, Positive Edge Triggered, 1-Bit, True Output, CMOS, PDSO6
Is it Rohs certified?	conform to	conform to
Maker	Nexperia	Nexperia
package instruction	SC-88,6 PIN	SC-74, 6 PIN
Reach Compliance Code	compliant	compliant
series	LVC/LCX/Z	LVC/LCX/Z
JESD-30 code	R-PDSO-G6	R-PDSO-G6
JESD-609 code	e3	e3
length	2 mm	2.9 mm
Logic integrated circuit type	D FLIP-FLOP	D FLIP-FLOP
Humidity sensitivity level	1	1
Number of digits	1	1
Number of functions	1	1
Number of terminals	6	6
Maximum operating temperature	125 °C	125 °C
Minimum operating temperature	-40 °C	-40 °C
Output polarity	TRUE	TRUE
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSSOP	TSSOP
Package shape	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	260	260
propagation delay (tpd)	17 ns	17 ns
Filter level	AEC-Q100	AEC-Q100
Maximum seat height	1.1 mm	1.1 mm
Maximum supply voltage (Vsup)	5.5 V	5.5 V
Minimum supply voltage (Vsup)	1.65 V	1.65 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	AUTOMOTIVE	AUTOMOTIVE
Terminal surface	Tin (Sn)	Tin (Sn)
Terminal form	GULL WING	GULL WING
Terminal pitch	0.65 mm	0.95 mm
Terminal location	DUAL	DUAL
Maximum time at peak reflow temperature	30	30
Trigger type	POSITIVE EDGE	POSITIVE EDGE
width	1.25 mm	1.5 mm
minfmax	200 MHz	200 MHz

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