BX80532KE083512 datasheet, PDF

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BX80532KE083512: DescriptionMicroprocessor, 64-Bit, 3.6MHz, CMOS, PBGA604, PLASTIC, FC--MPGA-604; CategoryThe embedded processor and controller Microcontrollers and processors; File Size4MB，140 Pages; ManufacturerIntel; Websitehttp://www.intel.com/

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BX80532KE083512 Overview

Microprocessor, 64-Bit, 3.6MHz, CMOS, PBGA604, PLASTIC, FC--MPGA-604

BX80532KE083512 Parametric

Parameter Name	Attribute value
Maker	Intel
Parts packaging code	PGA
package instruction	PGA,
Contacts	604
Reach Compliance Code	unknown
ECCN code	3A001.A.3
bit size	64
boundary scan	YES
maximum clock frequency	100 MHz
Format	FLOATING POINT
Integrated cache	YES
JESD-30 code	S-PBGA-P604
length	42.5 mm
low power mode	YES
Number of terminals	604
Package body material	PLASTIC/EPOXY
encapsulated code	PGA
Package shape	SQUARE
Package form	GRID ARRAY
speed	3.6 MHz
surface mount	NO
technology	CMOS
Terminal form	PIN/PEG
Terminal location	BOTTOM
width	42.5 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR

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Intel

Xeon

Processor E3-1200

Family

Datasheet, Volume 1

This is Volume 1 of 2

June 2011

Document Number: 324970-002

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED,

BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS

PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER,

AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING

LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY

PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

Legal Lines and Di scl aimers

UNLESS OTHERWISE AGREED IN WRITING BY INTEL, THE INTEL PRODUCTS ARE NOT DESIGNED NOR INTENDED FOR ANY

APPLICATION IN WHICH THE FAILURE OF THE INTEL PRODUCT COULD CREATE A SITUATION WHERE PERSONAL INJURY OR DEATH

MAY OCCUR.

Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the

absence or characteristics of any features or instructions marked

reserved or undefined.

Intel reserves these for future

definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The

information here is subject to change without notice. Do not finalize a design with this information.

The products described in this document may contain design defects or errors known as errata which may cause the product to

deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

All products, platforms, dates, and figures specified are preliminary based on current expectations, and are subject to change

without notice. All dates specified are target dates, are provided for planning purposes only and are subject to change.

This document contains information on products in the design phase of development. Do not finalize a design with this information.

Revised information will be published when the product is available. Verify with your local sales office that you have the latest

datasheet before finalizing a design.

No computer system can provide absolute security under all conditions. Intel

Trusted Execution Technology (Intel

TXT) requires

a computer system with Intel

Virtualization Technology, an Intel TXT-enabled processor, chipset, BIOS, Authenticated Code

Modules and an Intel TXT-compatible measured launched environment (MLE). The MLE could consist of a virtual machine monitor,

an OS or an application. In addition, Intel TXT requires the system to contain a TPM v1.2, as defined by the Trusted Computing

Group and specific software for some uses. For more information, see

http://www.intel.com/technology/security/

Intel

Virtualization Technology requires a computer system with an enabled Intel

processor, BIOS, virtual machine monitor

(VMM) and, for some uses, certain computer system software enabled for it. Functionality, performance or other benefits will vary

depending on hardware and software configurations and may require a BIOS update. Software applications may not be compatible

with all operating systems. Please check with your application vendor.

Intel

Active Management Technology requires the computer system to have an Intel(R) AMT-enabled chipset, network hardware

and software, as well as connection with a power source and a corporate network connection. Setup requires configuration by the

purchaser and may require scripting with the management console or further integration into existing security frameworks to

enable certain functionality. It may also require modifications of implementation of new business processes. With regard to

notebooks, Intel AMT may not be available or certain capabilities may be limited over a host OS-based VPN or when connecting

wirelessly, on battery power, sleeping, hibernating or powered off. For more information, see

http://www.intel.com/technology/

platform-technology/intel-amt/

Hyper-Threading Technology requires a computer system with a processor supporting HT Technology and an HT Technology-

enabled chipset, BIOS and operating system. Performance will vary depending on the specific hardware and software you use. For

more information including details on which processors support HT Technology, see htp://www.intel.com/info/hyperthreading.

Intel

Turbo Boost Technology requires a PC with a processor with Intel Turbo Boost Technology capability. Intel Turbo Boost

Technology performance varies depending on hardware, software and overall system configuration. Check with your PC

manufacturer on whether your system delivers Intel Turbo Boost Technology.For more information, see

http://www.intel.com/

technology/turboboost.

Enhanced Intel

SpeedStep

Technology See the Processor Spec Finder or contact your Intel representative for more information.

Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family,

not across different processor families. See

www.intel.com/products/processor_number for details.

64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, operating system, device

drivers and applications enabled for Intel

64 architecture. Performance will vary depending on your hardware and software

configurations. Consult with your system vendor for more information.

Code names featured are used internally within Intel to identify products that are in development and not yet publicly announced

for release. Customers, licensees and other third parties are not authorized by Intel to use code names in advertising, promotion or

marketing of any product or services and any such use of Intel's internal code names is at the sole risk of the user.

Intel, Intel Xeon, and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries.

*Other names and brands may be claimed as the property of others.

Datasheet, Volume 1

Contents

Introduction

.............................................................................................................. 9

1.1

Processor Feature Details ................................................................................... 11

1.1.1 Supported Technologies .......................................................................... 11

1.2

Interfaces ........................................................................................................ 11

1.2.1 System Memory Support ......................................................................... 11

1.2.2 PCI Express* ......................................................................................... 12

1.2.3 Direct Media Interface (DMI).................................................................... 14

1.2.4 Platform Environment Control Interface (PECI) ........................................... 14

1.2.5 Processor Graphics ................................................................................. 15

1.2.6 Intel

Flexible Display Interface (Intel

FDI) ............................................. 15

1.3

Power Management Support ............................................................................... 16

1.3.1 Processor Core....................................................................................... 16

1.3.2 System ................................................................................................. 16

1.3.3 Memory Controller.................................................................................. 16

1.3.4 PCI Express* ......................................................................................... 16

1.3.5 DMI...................................................................................................... 16

1.3.6 Processor Graphics Controller................................................................... 16

1.4

Thermal Management Support ............................................................................ 16

1.5

Package ........................................................................................................... 17

1.6

Terminology ..................................................................................................... 17

1.7

Related Documents ........................................................................................... 19

Interfaces................................................................................................................

2.1

System Memory Interface .................................................................................. 21

2.1.1 System Memory Technology Supported ..................................................... 21

2.1.2 System Memory Timing Support............................................................... 22

2.1.3 System Memory Organization Modes......................................................... 23

2.1.3.1 Single-Channel Mode................................................................. 23

2.1.3.2 Dual-Channel Mode Intel

Flex Memory Technology Mode ........... 23

2.1.4 Rules for Populating Memory Slots ............................................................ 24

2.1.5 Technology Enhancements of Intel

Fast Memory Access (Intel

FMA).......... 24

2.1.5.1 Just-in-Time Command Scheduling.............................................. 24

2.1.5.2 Command Overlap .................................................................... 24

2.1.5.3 Out-of-Order Scheduling ............................................................ 25

2.1.6 Memory Type Range Registers (MTRRs) Enhancement................................. 25

2.1.7 Data Scrambling .................................................................................... 25

2.2

PCI Express* Interface....................................................................................... 25

2.2.1 PCI Express* Architecture ....................................................................... 25

2.2.1.1 Transaction Layer ..................................................................... 27

2.2.1.2 Data Link Layer ........................................................................ 27

2.2.1.3 Physical Layer .......................................................................... 27

2.2.2 PCI Express* Configuration Mechanism ..................................................... 28

2.2.3 PCI Express* Port................................................................................... 28

2.2.4 PCI Express Lanes Connection.................................................................. 29

2.3

Direct Media Interface (DMI)............................................................................... 29

2.3.1 DMI Error Flow....................................................................................... 29

2.3.2 Processor/PCH Compatibility Assumptions.................................................. 29

2.3.3 DMI Link Down ...................................................................................... 30

2.4

Processor Graphics Controller (GT) ...................................................................... 30

2.4.1 3D and Video Engines for Graphics Processing............................................ 31

2.4.1.1 3D Engine Execution Units ......................................................... 31

Datasheet, Volume 1

2.5

2.6

2.4.1.2 3D Pipeline ...............................................................................31

2.4.1.3 Video Engine ............................................................................32

2.4.1.4 2D Engine ................................................................................32

2.4.2 Processor Graphics Display ......................................................................33

2.4.2.1 Display Planes ..........................................................................33

2.4.2.2 Display Pipes ............................................................................34

2.4.2.3 Display Ports ............................................................................34

2.4.3 Intel

Flexible Display Interface ...............................................................34

2.4.4 Multi-Graphics Controller Multi-Monitor Support ..........................................34

Platform Environment Control Interface (PECI) ......................................................35

Interface Clocking..............................................................................................35

2.6.1 Internal Clocking Requirements ................................................................35

Technologies............................................................................................................37

3.1

Intel

Virtualization Technology ..........................................................................37

3.1.1 Intel

VT-x Objectives ............................................................................37

3.1.2 Intel

VT-x Features ...............................................................................38

3.1.3 Intel

VT-d Objectives ............................................................................38

3.1.4 Intel

VT-d Features ...............................................................................38

3.1.5 Intel

VT-d Features Not Supported..........................................................39

3.2

Intel

Trusted Execution Technology (Intel

TXT) .................................................40

3.3

Intel

Hyper-Threading Technology .....................................................................40

3.4

Intel

Turbo Boost Technology ............................................................................41

3.4.1 Intel

Turbo Boost Technology Frequency..................................................41

3.4.2 Intel

Turbo Boost Technology Graphics Frequency.....................................41

3.5

Intel

Advanced Vector Extensions (AVX) .............................................................42

3.6

Advanced Encryption Standard New Instructions (AES-NI) ......................................42

3.6.1 PCLMULQDQ Instruction ..........................................................................42

3.7

Intel

64 Architecture x2APIC .............................................................................42

Power Management

.................................................................................................45

4.1

Advanced Configuration and Power Interface (ACPI) States Supported ......................46

4.1.1 System States........................................................................................46

4.1.2 Processor Core/Package Idle States...........................................................46

4.1.3 Integrated Memory Controller States .........................................................46

4.1.4 PCIe Link States .....................................................................................46

4.1.5 DMI States ............................................................................................47

4.1.6 Processor Graphics Controller States .........................................................47

4.1.7 Interface State Combinations ...................................................................47

4.2

Processor Core Power Management ......................................................................48

4.2.1 Enhanced Intel

SpeedStep

Technology ..................................................48

4.2.2 Low-Power Idle States .............................................................................48

4.2.3 Requesting Low-Power Idle States ............................................................50

4.2.4 Core C-states .........................................................................................51

4.2.4.1 Core C0 State ...........................................................................51

4.2.4.2 Core C1/C1E State ....................................................................51

4.2.4.3 Core C3 State ...........................................................................51

4.2.4.4 Core C6 State ...........................................................................51

4.2.4.5 C-State Auto-Demotion ..............................................................51

4.2.5 Package C-States ...................................................................................52

4.2.5.1 Package C0 ..............................................................................53

4.2.5.2 Package C1/C1E........................................................................53

4.2.5.3 Package C3 State ......................................................................54

4.2.5.4 Package C6 State ......................................................................54

4.3

IMC Power Management .....................................................................................54

4.3.1 Disabling Unused System Memory Outputs.................................................54

4.3.2 DRAM Power Management and Initialization ...............................................55

Datasheet, Volume 1

4.4

4.5

4.6

4.7

4.3.2.1 Initialization Role of CKE ............................................................ 56

4.3.2.2 Conditional Self-Refresh ............................................................ 56

4.3.2.3 Dynamic Power-down Operation ................................................. 57

4.3.2.4 DRAM I/O Power Management .................................................... 57

PCIe* Power Management .................................................................................. 57

DMI Power Management..................................................................................... 57

Graphics Power Management .............................................................................. 58

4.6.1 Intel

Rapid Memory Power Management (Intel

RMPM)

(also known as CxSR) ............................................................................. 58

4.6.2 Intel

Graphics Performance Modulation Technology (Intel

GPMT) .............. 58

4.6.3 Graphics Render C-State ......................................................................... 58

4.6.4 Intel

Smart 2D Display Technology (Intel

S2DDT) .................................. 58

4.6.5 Intel

Graphics Dynamic Frequency.......................................................... 59

Thermal Power Management ............................................................................... 59

Thermal Management

.............................................................................................. 61

Signal Description

................................................................................................... 63

6.1

System Memory Interface .................................................................................. 64

6.2

Memory Reference and Compensation.................................................................. 65

6.3

Reset and Miscellaneous Signals .......................................................................... 66

6.4

PCI Express* Based Interface Signals................................................................... 67

6.5

Intel

Flexible Display Interface Signals ............................................................... 67

6.6

DMI................................................................................................................. 67

6.7

PLL Signals ....................................................................................................... 68

6.8

TAP Signals ...................................................................................................... 68

6.9

Error and Thermal Protection .............................................................................. 69

6.10 Power Sequencing ............................................................................................. 69

6.11 Processor Power Signals ..................................................................................... 70

6.12 Sense Pins ....................................................................................................... 70

6.13 Ground and NCTF .............................................................................................. 70

6.14 Processor Internal Pull Up/Pull Down.................................................................... 71

Electrical Specifications

........................................................................................... 73

7.1

Power and Ground Lands.................................................................................... 73

7.2

Decoupling Guidelines ........................................................................................ 73

7.2.1 Voltage Rail Decoupling........................................................................... 73

7.3

Processor Clocking (BCLK[0], BCLK#[0]) .............................................................. 74

7.3.1 PLL Power Supply ................................................................................... 74

7.4

Voltage Identification (VID) .......................................................................... 74

7.5

System Agent (SA) VCC VID ............................................................................... 78

7.6

Reserved or Unused Signals................................................................................ 78

7.7

Signal Groups ................................................................................................... 79

7.8

Test Access Port (TAP) Connection....................................................................... 80

7.9

Storage Conditions Specifications ........................................................................ 81

7.10 DC Specifications .............................................................................................. 82

7.10.1 Voltage and Current Specifications............................................................ 82

7.11 Platform Environmental Control Interface (PECI) DC Specifications........................... 87

7.11.1 PECI Bus Architecture ............................................................................. 87

7.11.2 DC Characteristics .................................................................................. 88

7.11.3 Input Device Hysteresis .......................................................................... 88

Processor Pin and Signal Information......................................................................

8.1

Processor Pin Assignments ................................................................................. 89

DDR Data Swizzling

............................................................................................... 109

Datasheet, Volume 1

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Description	Microprocessor, 64-Bit, 3.6MHz, CMOS, PBGA604, PLASTIC, FC--MPGA-604	Microprocessor, 64-Bit, 3060MHz, CMOS, PBGA604, PLASTIC, FC--MPGA-604	Microprocessor, 64-Bit, 2800MHz, CMOS, PBGA604, PLASTIC, FC--MPGA-604	Microprocessor, 64-Bit, 2800MHz, CMOS, PBGA604, PLASTIC, FC--MPGA-604	Microprocessor, 64-Bit, 3060MHz, CMOS, PBGA604, PLASTIC, FC--MPGA-604	Microprocessor, 64-Bit, 3200MHz, CMOS, PBGA604, PLASTIC, FC--MPGA-604	Microprocessor, 64-Bit, 3060MHz, CMOS, PBGA604, PLASTIC, FC--MPGA-604	Microprocessor, 64-Bit, 3200MHz, CMOS, PBGA604, PLASTIC, FC--MPGA-604	Microprocessor, 64-Bit, 3200MHz, CMOS, PBGA604, PLASTIC, FC--MPGA-604	Microprocessor, 64-Bit, 2800MHz, CMOS, PBGA604, PLASTIC, FC--MPGA-604
Maker	Intel	Intel	Intel	Intel	Intel	Intel	Intel	Intel	Intel	Intel
Parts packaging code	PGA	PGA	PGA	PGA	PGA	PGA	PGA	PGA	PGA	PGA
package instruction	PGA,	PGA,	PGA,	PGA,	PGA, PGA603,25X31,50	PGA,	PGA,	PGA, PGA604,25X31,50	PGA, PGA604,25X31,50	PGA, PGA604,25X31,50
Contacts	604	604	604	604	604	604	604	604	604	604
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown
ECCN code	3A001.A.3	3A001.A.3	3A001.A.3	3A001.A.3	3A001.A.3	3A001.A.3	3A001.A.3	3A001.A.3	3A001.A.3	3A001.A.3
bit size	64	64	64	64	64	64	64	64	64	64
boundary scan	YES	YES	YES	YES	YES	YES	YES	YES	YES	YES
maximum clock frequency	100 MHz	100 MHz	100 MHz	100 MHz	100 MHz	100 MHz	100 MHz	100 MHz	100 MHz	100 MHz
Format	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT	FLOATING POINT
Integrated cache	YES	YES	YES	YES	YES	YES	YES	YES	YES	YES
JESD-30 code	S-PBGA-P604	S-PBGA-P604	S-PBGA-P604	S-PBGA-P604	S-PBGA-P604	S-PBGA-P604	S-PBGA-P604	S-PBGA-P604	S-PBGA-P604	S-PBGA-P604
length	42.5 mm	42.5 mm	42.5 mm	42.5 mm	42.5 mm	42.5 mm	42.5 mm	42.5 mm	42.5 mm	42.5 mm
low power mode	YES	YES	YES	YES	YES	YES	YES	YES	YES	YES
Number of terminals	604	604	604	604	604	604	604	604	604	604
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	PGA	PGA	PGA	PGA	PGA	PGA	PGA	PGA	PGA	PGA
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY	GRID ARRAY
speed	3.6 MHz	3060 MHz	2800 MHz	2800 MHz	3060 MHz	3200 MHz	3060 MHz	3200 MHz	3200 MHz	2800 MHz
surface mount	NO	NO	NO	NO	NO	NO	NO	NO	NO	NO
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Terminal form	PIN/PEG	PIN/PEG	PIN/PEG	PIN/PEG	PIN/PEG	PIN/PEG	PIN/PEG	PIN/PEG	PIN/PEG	PIN/PEG
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
width	42.5 mm	42.5 mm	42.5 mm	42.5 mm	42.5 mm	42.5 mm	42.5 mm	42.5 mm	42.5 mm	42.5 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR	MICROPROCESSOR

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Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

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